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-rw-r--r--src/mainboard/intel/cedarisland_crb/bootblock.c2
-rw-r--r--src/mainboard/ocp/tiogapass/bootblock.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/cedarisland_crb/bootblock.c b/src/mainboard/intel/cedarisland_crb/bootblock.c
index e51752b371..ae8212a8dd 100644
--- a/src/mainboard/intel/cedarisland_crb/bootblock.c
+++ b/src/mainboard/intel/cedarisland_crb/bootblock.c
@@ -21,7 +21,7 @@ void bootblock_mainboard_early_init(void)
pcr_write32(PID_DMI, 0x2774, 1);
/* Decode for SuperIO (0x2e) and COM1 (0x3f8) */
- pci_mmio_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16));
+ pci_s_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16));
const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1);
aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c
index b5c2aa1567..6bcbfcc473 100644
--- a/src/mainboard/ocp/tiogapass/bootblock.c
+++ b/src/mainboard/ocp/tiogapass/bootblock.c
@@ -30,7 +30,7 @@ static void enable_espi_lpc_io_windows(void)
pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1));
/* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
- pci_mmio_write_config32(PCH_DEV_LPC, 0x80,
+ pci_s_write_config32(PCH_DEV_LPC, 0x80,
(1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4));
}