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-rw-r--r--src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
index 2e001c6481..0b789146ae 100644
--- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
@@ -22,7 +22,7 @@ chip soc/intel/tigerlake
register "enable_c6dram" = "1"
register "HeciEnabled" = "1"
register "SaGv" = "SaGv_Enabled"
- register "TcssD3ColdDisable" = "1"
+ register "TcssD3ColdDisable" = "1"
# FSP Silicon
# Serial I/O