4 files changed, 44 insertions, 0 deletions
diff --git a/src/mainboard/intel/archercity_crb/Makefile.mk b/src/mainboard/intel/archercity_crb/Makefile.mk
index 4c7a7beee1..b28d73c27a 100644
--- a/src/mainboard/intel/archercity_crb/Makefile.mk
+++ b/src/mainboard/intel/archercity_crb/Makefile.mk
@@ -2,5 +2,7 @@
 
 bootblock-y += bootblock.c
 romstage-y += romstage.c
+romstage-y += util.c
 ramstage-y += ramstage.c
+ramstage-y += util.c
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/intel/archercity_crb/util.c b/src/mainboard/intel/archercity_crb/util.c
new file mode 100644
index 0000000000..5197b23292
--- /dev/null
+++ b/src/mainboard/intel/archercity_crb/util.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/ocp/include/vpd.h>
+#include <soc/chip_common.h>
+#include <soc/util.h>
+
+#if CONFIG(SOC_INTEL_HAS_CXL)
+enum xeonsp_cxl_mode get_cxl_mode(void)
+{
+	int ocp_cxl_mode = get_cxl_mode_from_vpd();
+	switch (ocp_cxl_mode) {
+	case CXL_SYSTEM_MEMORY:
+		return XEONSP_CXL_SYS_MEM;
+	case CXL_SPM:
+		return XEONSP_CXL_SP_MEM;
+	default:
+		return XEONSP_CXL_DISABLED;
+	}
+}
+#endif
diff --git a/src/mainboard/inventec/transformers/Makefile.mk b/src/mainboard/inventec/transformers/Makefile.mk
index ecb6ef2217..eb859d3d69 100644
--- a/src/mainboard/inventec/transformers/Makefile.mk
+++ b/src/mainboard/inventec/transformers/Makefile.mk
@@ -2,5 +2,7 @@
 
 bootblock-y += bootblock.c
 romstage-y += romstage.c
+romstage-y += util.c
 romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi.c
+ramstage-y += util.c
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/inventec/transformers/util.c b/src/mainboard/inventec/transformers/util.c
new file mode 100644
index 0000000000..5197b23292
--- /dev/null
+++ b/src/mainboard/inventec/transformers/util.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/ocp/include/vpd.h>
+#include <soc/chip_common.h>
+#include <soc/util.h>
+
+#if CONFIG(SOC_INTEL_HAS_CXL)
+enum xeonsp_cxl_mode get_cxl_mode(void)
+{
+	int ocp_cxl_mode = get_cxl_mode_from_vpd();
+	switch (ocp_cxl_mode) {
+	case CXL_SYSTEM_MEMORY:
+		return XEONSP_CXL_SYS_MEM;
+	case CXL_SPM:
+		return XEONSP_CXL_SP_MEM;
+	default:
+		return XEONSP_CXL_DISABLED;
+	}
+}
+#endif