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-rw-r--r--src/mainboard/google/gru/Kconfig5
-rw-r--r--src/mainboard/google/gru/devicetree.scarlet.cb20
2 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig
index 43f671b600..feb14c0bcb 100644
--- a/src/mainboard/google/gru/Kconfig
+++ b/src/mainboard/google/gru/Kconfig
@@ -83,6 +83,11 @@ config CONSOLE_SERIAL_UART_ADDRESS
##########################################################
#### Update below when adding a new derivative board. ####
##########################################################
+config DEVICETREE
+ string
+ default "devicetree.scarlet.cb" if BOARD_GOOGLE_SCARLET
+ default "devicetree.cb"
+
config MAINBOARD_PART_NUMBER
string
default "Scarlet" if BOARD_GOOGLE_SCARLET
diff --git a/src/mainboard/google/gru/devicetree.scarlet.cb b/src/mainboard/google/gru/devicetree.scarlet.cb
new file mode 100644
index 0000000000..2c316545f0
--- /dev/null
+++ b/src/mainboard/google/gru/devicetree.scarlet.cb
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2017 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip soc/rockchip/rk3399
+ device cpu_cluster 0 on end
+ register "vop_mode" = "VOP_MODE_NONE"
+ register "framebuffer_bits_per_pixel" = "32"
+end