summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index d5f58bae3e..0efb76dfe0 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -76,6 +76,31 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
+ # PCIE Root Port Configuration
+ register "PcieRpEnable[0]" = "0"
+ register "PcieRpEnable[1]" = "0"
+ register "PcieRpEnable[2]" = "0"
+ register "PcieRpEnable[3]" = "0"
+ register "PcieRpEnable[4]" = "0"
+ register "PcieRpEnable[5]" = "0"
+ register "PcieRpEnable[6]" = "0"
+ register "PcieRpEnable[7]" = "0"
+
+ register "PcieClkSrcUsage[0]" = "0xff"
+ register "PcieClkSrcUsage[1]" = "0xff"
+ register "PcieClkSrcUsage[2]" = "0xff"
+ register "PcieClkSrcUsage[3]" = "0xff"
+ register "PcieClkSrcUsage[4]" = "0xff"
+ register "PcieClkSrcUsage[5]" = "0xff"
+
+ # PCIE Clock Request to Clock Source Mapping
+ register "PcieClkSrcClkReq[0]" = "0"
+ register "PcieClkSrcClkReq[1]" = "1"
+ register "PcieClkSrcClkReq[2]" = "2"
+ register "PcieClkSrcClkReq[3]" = "3"
+ register "PcieClkSrcClkReq[4]" = "4"
+ register "PcieClkSrcClkReq[5]" = "5"
+
# Enable EMMC HS400 mode
register "ScsEmmcHs400Enabled" = "1"