diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/skyrim/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/skyrim/port_descriptors.c | 4 | ||||
| -rw-r--r-- | src/mainboard/google/skyrim/variants/baseboard/devicetree.cb | 8 |
3 files changed, 10 insertions, 3 deletions
diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index a89cc82d77..53cdce2a6f 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_I2C_NAU8825 select DRIVERS_USB_HUB select DRIVERS_UART_ACPI + select DRIVERS_PCIE_RTD3_DEVICE select DRIVERS_PCIE_GENERIC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ESPI diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c index 3af2d858fc..d745bd7e1d 100644 --- a/src/mainboard/google/skyrim/port_descriptors.c +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -28,7 +28,7 @@ static const fsp_dxio_descriptor skyrim_mdn_dxio_descriptors[] = { .function_number = PCI_FUNC(SD_DEVFN), .link_speed_capability = GEN3, .turn_off_unused_lanes = true, - .link_aspm = ASPM_DISABLED, // TODO: switch to ASPM_L1 after b:245550573 + .link_aspm = ASPM_L1, .link_hotplug = 3, .gpio_group_id = GPIO_27, .clk_req = CLK_REQ1, @@ -42,7 +42,7 @@ static const fsp_dxio_descriptor skyrim_mdn_dxio_descriptors[] = { .function_number = PCI_FUNC(NVME_DEVFN), .link_speed_capability = GEN3, .turn_off_unused_lanes = true, - .link_aspm = ASPM_DISABLED, // TODO: switch to ASPM_L1 after b:245550573 + .link_aspm = ASPM_L1, .link_hotplug = 3, .gpio_group_id = GPIO_6, .clk_req = CLK_REQ0, diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 3b98246d19..52019abf30 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -99,7 +99,13 @@ chip soc/amd/mendocino end device ref iommu on end device ref gpp_bridge_1 on end # SD - device ref gpp_bridge_2 on end # NVMe + device ref gpp_bridge_2 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) |