diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/kinox/gpio.c | 6 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/kinox/overridetree.cb | 14 |
2 files changed, 18 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/kinox/gpio.c b/src/mainboard/google/brya/variants/kinox/gpio.c index 0fbfee03e6..fa63c1d8ec 100644 --- a/src/mainboard/google/brya/variants/kinox/gpio.c +++ b/src/mainboard/google/brya/variants/kinox/gpio.c @@ -41,7 +41,7 @@ static const struct pad_config override_gpio_table[] = { /* D17 : UART1_RXD ==> NC */ PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* D18 : UART1_TXD ==> EMMC_PE_RST_L */ - PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), + PAD_CFG_GPO(GPP_D18, 1, DEEP), /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ /* E4 : SATA_DEVSLP0 ==> USB_A1_RT_RST_ODL */ @@ -93,6 +93,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* D18 : UART1_TXD ==> EMMC_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* F14 : GSXDIN ==> EN_PP3300_SSD */ @@ -107,7 +109,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + /* H13 : I2C7_SCL ==> EN_PP3300_EMMC */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* CPU PCIe VGPIO for PEG60 */ diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index a4050eef39..96e621e46c 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -187,6 +187,20 @@ chip soc/intel/alderlake device generic 0 alias dptf_policy on end end end + device ref pcie_rp6 on + # Enable PCIe-to-eMMC bridge PCIE 6 using clk 1 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "1" + device generic 0 alias emmc_rtd3 on end + end + end # BH799BBLN device ref pcie_rp7 on chip drivers/net register "customized_leds" = "0x05af" |