diff options
Diffstat (limited to 'src/mainboard')
35 files changed, 0 insertions, 2480 deletions
diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig deleted file mode 100644 index f67f9b0e04..0000000000 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ /dev/null @@ -1,61 +0,0 @@ -if BOARD_INTEL_COUGAR_CANYON2 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_FSP_IVYBRIDGE - select SOUTHBRIDGE_INTEL_FSP_BD82X6X - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select SUPERIO_SMSC_SIO1007 - select ENABLE_VMX - select INTEL_INT15 - select VGA - -config MAINBOARD_DIR - string - default intel/cougar_canyon2 - -config MAINBOARD_PART_NUMBER - string - default "Cougar Canyon 2" - -config MMCONF_BASE_ADDRESS - hex - default 0xf8000000 # set to match FSP - -config MAX_CPUS - int - default 16 - -config SMBIOS_ENCLOSURE_TYPE - hex - default 0x09 # This is a mobile platform - -config UDELAY_LAPIC_FIXED_FSB - int - default 100 - -config VIRTUAL_ROM_SIZE - hex - default 0x1000000 - -if HAVE_FSP_BIN - -config VGA_BIOS - bool - default y - -config VGA_BIOS_FILE - string - default "../intel/mainboard/intel/cougar_canyon2/vbios/snm_2170.dat" - -config VGA_BIOS_ID - string - default "8086,0166" - - -endif # HAVE_FSP_BIN - -endif # BOARD_INTEL_COUGAR_CANYON2 diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig.name b/src/mainboard/intel/cougar_canyon2/Kconfig.name deleted file mode 100644 index b2c8c1cb75..0000000000 --- a/src/mainboard/intel/cougar_canyon2/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_COUGAR_CANYON2 - bool "Cougar Canyon 2 CRB" diff --git a/src/mainboard/intel/cougar_canyon2/acpi/ec.asl b/src/mainboard/intel/cougar_canyon2/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 --- a/src/mainboard/intel/cougar_canyon2/acpi/ec.asl +++ /dev/null diff --git a/src/mainboard/intel/cougar_canyon2/acpi/hostbridge_pci_irqs.asl b/src/mainboard/intel/cougar_canyon2/acpi/hostbridge_pci_irqs.asl deleted file mode 100644 index 829dd7ccf4..0000000000 --- a/src/mainboard/intel/cougar_canyon2/acpi/hostbridge_pci_irqs.asl +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 19 }, - - // Network 0:19.0 - Package() { 0x0019ffff, 0, 0, 20 }, - - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 }, - - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - - /* MEI */ - Package() { 0x0016ffff, 0, 0, 16 }, - Package() { 0x0016ffff, 1, 0, 17 }, - - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 23 }, - - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 16 }, - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 2, 0, 18 }, - Package() { 0x001fffff, 3, 0, 16 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - - // EHCI #2 0:19.0 - Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - - /* Management Engine Interface */ - Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/intel/cougar_canyon2/acpi/mainboard.asl b/src/mainboard/intel/cougar_canyon2/acpi/mainboard.asl deleted file mode 100644 index c43d2dba7d..0000000000 --- a/src/mainboard/intel/cougar_canyon2/acpi/mainboard.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) - - // Wake - Name(_PRW, Package(){0x1d, 0x05}) -} diff --git a/src/mainboard/intel/cougar_canyon2/acpi/platform.asl b/src/mainboard/intel/cougar_canyon2/acpi/platform.asl deleted file mode 100644 index c0a60aa2f3..0000000000 --- a/src/mainboard/intel/cougar_canyon2/acpi/platform.asl +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ - // NVS has a flag to determine USB policy in S3 - if (S3U0) { - Store (One, GP47) // Enable USB0 - } Else { - Store (Zero, GP47) // Disable USB0 - } - - // NVS has a flag to determine USB policy in S3 - if (S3U1) { - Store (One, GP56) // Enable USB1 - } Else { - Store (Zero, GP56) // Disable USB1 - } -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/intel/cougar_canyon2/acpi/superio.asl b/src/mainboard/intel/cougar_canyon2/acpi/superio.asl deleted file mode 100644 index 07e41873a7..0000000000 --- a/src/mainboard/intel/cougar_canyon2/acpi/superio.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Values should match those defined in devicetree.cb */ - -#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller -#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR - -#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse -#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 -#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller -#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 -#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 -#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO -#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 -#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 - -#include <superio/smsc/sio1007/acpi/superio.asl> diff --git a/src/mainboard/intel/cougar_canyon2/acpi_tables.c b/src/mainboard/intel/cougar_canyon2/acpi_tables.c deleted file mode 100644 index 40771dfa5a..0000000000 --- a/src/mainboard/intel/cougar_canyon2/acpi_tables.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <southbridge/intel/fsp_bd82x6x/nvs.h> - -#include "thermal.h" - -static global_nvs_t *gnvs_; - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; - gnvs->flvl = 5; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - gnvs_ = gnvs; - memset((void *)gnvs, 0, sizeof(*gnvs)); - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* - * Enable Front USB ports in S5 by default - * to be consistent with back port behavior - */ - gnvs->s5u0 = 1; - gnvs->s5u1 = 1; - - acpi_update_thermal_table(gnvs); -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/mainboard/intel/cougar_canyon2/board_info.txt b/src/mainboard/intel/cougar_canyon2/board_info.txt deleted file mode 100644 index b89835dfc8..0000000000 --- a/src/mainboard/intel/cougar_canyon2/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: eval -Release year: 2010 diff --git a/src/mainboard/intel/cougar_canyon2/cmos.layout b/src/mainboard/intel/cougar_canyon2/cmos.layout deleted file mode 100644 index 70ce406b6c..0000000000 --- a/src/mainboard/intel/cougar_canyon2/cmos.layout +++ /dev/null @@ -1,105 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode -#412 4 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb deleted file mode 100644 index d7c6aabd4e..0000000000 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ /dev/null @@ -1,70 +0,0 @@ -chip northbridge/intel/fsp_sandybridge - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - # Enable DisplayPort 1 Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable DisplayPort 0 Hotplug with 6ms pulse - register "gpu_dp_c_hotplug" = "0x06" - - # Enable DVI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end - chip cpu/intel/fsp_model_206ax - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - - chip southbridge/intel/fsp_bd82x6x # Intel Series 6 Cougar Point PCH - register "sata_port_map" = "0x3f" - - register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" - - device pci 14.0 on end # XHCI - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 on end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 on end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge - # TODO: insert SIO UART and WDT - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # SATA Controller 2 - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/intel/cougar_canyon2/dsdt.asl b/src/mainboard/intel/cougar_canyon2/dsdt.asl deleted file mode 100644 index d167e4e4f8..0000000000 --- a/src/mainboard/intel/cougar_canyon2/dsdt.asl +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - #include <southbridge/intel/bd82x6x/acpi/platform.asl> - - // Some generic macros - #include "acpi/platform.asl" - - // global NVS and variables - #include <southbridge/intel/fsp_bd82x6x/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - #include <cpu/intel/fsp_model_206ax/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl> - #include <southbridge/intel/fsp_bd82x6x/acpi/pch.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - } - - /* Chipset specific sleep states */ - #include <southbridge/intel/fsp_bd82x6x/acpi/sleepstates.asl> -} diff --git a/src/mainboard/intel/cougar_canyon2/gpio.h b/src/mainboard/intel/cougar_canyon2/gpio.h deleted file mode 100644 index b4e3915e70..0000000000 --- a/src/mainboard/intel/cougar_canyon2/gpio.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include <southbridge/intel/fsp_bd82x6x/gpio.h> - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* SINAI */ - .gpio1 = GPIO_MODE_GPIO, /* SMC_SMI */ - .gpio2 = GPIO_MODE_GPIO, /* PIRQE# */ - .gpio3 = GPIO_MODE_GPIO, /* PIRQF# */ - .gpio4 = GPIO_MODE_GPIO, /* PIRQG# */ - .gpio5 = GPIO_MODE_GPIO, /* PIRQH# */ - .gpio6 = GPIO_MODE_GPIO, /* DGPU_HPD_INTR*/ - .gpio7 = GPIO_MODE_GPIO, /* SMC_SCI# */ - .gpio8 = GPIO_MODE_NONE, /* NOT USED */ - .gpio9 = GPIO_MODE_NATIVE, /* USB OC10-11*/ - .gpio10 = GPIO_MODE_NATIVE, /* USB OC12-13 */ - .gpio11 = GPIO_MODE_GPIO, /* SMB_ALERT*/ - .gpio12 = GPIO_MODE_NATIVE, /* LAN DISABLE */ - .gpio13 = GPIO_MODE_NATIVE, /* HDA_DOCK_RST */ - .gpio14 = GPIO_MODE_GPIO, /* SMC_WAKE */ - .gpio15 = GPIO_MODE_GPIO, /* HOST ALERT */ - .gpio16 = GPIO_MODE_NATIVE, /* SATA4GP */ - .gpio17 = GPIO_MODE_GPIO, /* DGPU POWEROK */ - .gpio18 = GPIO_MODE_NATIVE, /* PCIECLKRQ1# */ - .gpio19 = GPIO_MODE_NATIVE, /* BBS0 */ - .gpio20 = GPIO_MODE_NATIVE, /* CIECLKRQ2# */ - .gpio21 = GPIO_MODE_NATIVE, /* SATA0GP */ - .gpio22 = GPIO_MODE_GPIO, /* BIOS Recovery */ - .gpio23 = GPIO_MODE_NATIVE, /* LDRQ1 */ - .gpio24 = GPIO_MODE_NONE, /* HOST ALERT */ - .gpio25 = GPIO_MODE_NATIVE, /* PCIECLKRQ3# */ - .gpio26 = GPIO_MODE_NATIVE, /* PCIECLKRQ4# */ - .gpio27 = GPIO_MODE_GPIO, /* SATA0 PWR EN */ - .gpio28 = GPIO_MODE_GPIO, /* PLL ODVR */ - .gpio29 = GPIO_MODE_GPIO, /* SLP_LAN# */ - .gpio30 = GPIO_MODE_NATIVE, /* SUS_WARN# */ - .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_OUTPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_OUTPUT, - .gpio13 = GPIO_DIR_OUTPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio18 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio20 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio23 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio25 = GPIO_DIR_INPUT, - .gpio26 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_OUTPUT, - .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_OUTPUT, - .gpio30 = GPIO_DIR_OUTPUT, - .gpio31 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, - .gpio1 = GPIO_LEVEL_HIGH, - .gpio2 = GPIO_LEVEL_HIGH, - .gpio3 = GPIO_LEVEL_HIGH, - .gpio4 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_LOW, - .gpio6 = GPIO_LEVEL_HIGH, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_HIGH, - .gpio9 = GPIO_LEVEL_HIGH, - .gpio10 = GPIO_LEVEL_HIGH, - .gpio11 = GPIO_LEVEL_HIGH, - .gpio12 = GPIO_LEVEL_HIGH, - .gpio13 = GPIO_LEVEL_LOW, - .gpio14 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_HIGH, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_LOW, - .gpio18 = GPIO_LEVEL_HIGH, - .gpio19 = GPIO_LEVEL_HIGH, - .gpio20 = GPIO_LEVEL_HIGH, - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, - .gpio25 = GPIO_LEVEL_HIGH, - .gpio26 = GPIO_LEVEL_HIGH, - .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_HIGH, - .gpio30 = GPIO_LEVEL_HIGH, - .gpio31 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio1 = GPIO_INVERT, - .gpio3 = GPIO_INVERT, - .gpio7 = GPIO_INVERT, - .gpio14 = GPIO_INVERT, - .gpio15 = GPIO_INVERT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* SIO CLKREQ */ - .gpio33 = GPIO_MODE_NATIVE, /* DOCK ENABLE*/ - .gpio34 = GPIO_MODE_GPIO, /* STP PCI LED */ - .gpio35 = GPIO_MODE_NATIVE, /* SATA POWER EN */ - .gpio36 = GPIO_MODE_NATIVE, /* SATA2 PRESENT DET */ - .gpio37 = GPIO_MODE_NONE, /* NOT USED */ - .gpio38 = GPIO_MODE_GPIO, /* MFG MODE */ - .gpio39 = GPIO_MODE_GPIO, /* GP39 GFX CRB DET */ - .gpio40 = GPIO_MODE_NATIVE, /* USB OC 2-3 */ - .gpio41 = GPIO_MODE_NATIVE, /* USB OC 4-5 */ - .gpio42 = GPIO_MODE_NATIVE, /* USB OC 6-7 */ - .gpio43 = GPIO_MODE_NATIVE, /* USB OC 8-9 */ - .gpio44 = GPIO_MODE_NATIVE, /* PCI SLOT5 CLKREQ5 */ - .gpio45 = GPIO_MODE_NATIVE, /* LAN CLKREQ6 */ - .gpio46 = GPIO_MODE_GPIO, /* PCI SLOT5 CLKREQ5 */ - .gpio47 = GPIO_MODE_NATIVE, /* PEG CLKREQ7 */ - .gpio48 = GPIO_MODE_GPIO, /* SV_ADVANCE_GP48 */ - .gpio49 = GPIO_MODE_GPIO, /* CRIT_TEMP */ - .gpio50 = GPIO_MODE_GPIO, /* DGPU RESET */ - .gpio51 = GPIO_MODE_NONE, /* NOT USED */ - .gpio52 = GPIO_MODE_GPIO, /* DGPU SEL */ - .gpio53 = GPIO_MODE_GPIO, /* DGPU PWM SEL */ - .gpio54 = GPIO_MODE_GPIO, /* DGPU PWM EN */ - .gpio55 = GPIO_MODE_NONE, /* NOT USED */ - .gpio56 = GPIO_MODE_NATIVE, /* NOT USED */ - .gpio57 = GPIO_MODE_NATIVE, /* GP57_SV_DETECT */ - .gpio58 = GPIO_MODE_NATIVE, /* SML1CLK_PCH */ - .gpio59 = GPIO_MODE_NATIVE, /* USB OC 0-1 */ - .gpio60 = GPIO_MODE_GPIO, /* DDR RST CTRL */ - .gpio61 = GPIO_MODE_NATIVE, /* LPC SUSTAT */ - .gpio62 = GPIO_MODE_NATIVE, /* LPC SUSCLK */ - .gpio63 = GPIO_MODE_NATIVE, /* SLP S5*/ - -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_OUTPUT, - .gpio34 = GPIO_DIR_OUTPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_OUTPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio44 = GPIO_DIR_INPUT, - .gpio45 = GPIO_DIR_INPUT, - .gpio46 = GPIO_DIR_OUTPUT, - .gpio47 = GPIO_DIR_INPUT, - .gpio48 = GPIO_DIR_INPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio50 = GPIO_DIR_OUTPUT, - .gpio51 = GPIO_DIR_OUTPUT, - .gpio52 = GPIO_DIR_OUTPUT, - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_OUTPUT, - .gpio55 = GPIO_DIR_OUTPUT, - .gpio56 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, - .gpio61 = GPIO_DIR_OUTPUT, - .gpio62 = GPIO_DIR_OUTPUT, - .gpio63 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, - .gpio33 = GPIO_LEVEL_HIGH, - .gpio34 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_HIGH, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_HIGH, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_HIGH, - .gpio41 = GPIO_LEVEL_HIGH, - .gpio42 = GPIO_LEVEL_HIGH, - .gpio43 = GPIO_LEVEL_HIGH, - .gpio44 = GPIO_LEVEL_HIGH, - .gpio45 = GPIO_LEVEL_HIGH, - .gpio46 = GPIO_LEVEL_HIGH, - .gpio47 = GPIO_LEVEL_LOW, - .gpio48 = GPIO_LEVEL_HIGH, - .gpio49 = GPIO_LEVEL_HIGH, - .gpio50 = GPIO_LEVEL_HIGH, - .gpio51 = GPIO_LEVEL_HIGH, - .gpio52 = GPIO_LEVEL_HIGH, - .gpio53 = GPIO_LEVEL_HIGH, - .gpio54 = GPIO_LEVEL_HIGH, - .gpio55 = GPIO_LEVEL_LOW, - .gpio56 = GPIO_LEVEL_HIGH, - .gpio57 = GPIO_LEVEL_LOW, - .gpio58 = GPIO_LEVEL_HIGH, - .gpio59 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_HIGH, - .gpio62 = GPIO_LEVEL_HIGH, - .gpio63 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NATIVE, /* CLK_FLEX0 */ - .gpio65 = GPIO_MODE_NATIVE, /* NOT USED / CLK_FLEX1 */ - .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 */ - .gpio67 = GPIO_MODE_GPIO, /* GPU PRSNT */ - .gpio68 = GPIO_MODE_GPIO, /* SATA PORT2 PWR EN*/ - .gpio69 = GPIO_MODE_GPIO, /* TESTMODE */ - .gpio70 = GPIO_MODE_NATIVE, /* USB3 SLOT 2DET */ - .gpio71 = GPIO_MODE_NATIVE, /* USB3 SLOT 1 DET */ - .gpio72 = GPIO_MODE_NATIVE, /* BATLOW# */ - .gpio73 = GPIO_MODE_NATIVE, /* PCIECLKRQ0#*/ - .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT# /PCHHOT# */ - .gpio75 = GPIO_MODE_NATIVE, /* SML1DATA */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_OUTPUT, - .gpio65 = GPIO_DIR_OUTPUT, - .gpio66 = GPIO_DIR_OUTPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_OUTPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio70 = GPIO_DIR_INPUT, - .gpio71 = GPIO_DIR_INPUT, - .gpio72 = GPIO_DIR_INPUT, - .gpio73 = GPIO_DIR_INPUT, - .gpio74 = GPIO_DIR_INPUT, - .gpio75 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_HIGH, - .gpio65 = GPIO_LEVEL_HIGH, - .gpio66 = GPIO_LEVEL_LOW, - .gpio67 = GPIO_LEVEL_HIGH, - .gpio68 = GPIO_LEVEL_HIGH, - .gpio69 = GPIO_LEVEL_HIGH, - .gpio70 = GPIO_LEVEL_HIGH, - .gpio71 = GPIO_LEVEL_HIGH, - .gpio72 = GPIO_LEVEL_HIGH, - .gpio73 = GPIO_LEVEL_HIGH, - .gpio74 = GPIO_LEVEL_HIGH, - .gpio75 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_map gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/intel/cougar_canyon2/hda_verb.c b/src/mainboard/intel/cougar_canyon2/hda_verb.c deleted file mode 100644 index 92cb23441f..0000000000 --- a/src/mainboard/intel/cougar_canyon2/hda_verb.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x80862805, // Codec Vendor / Device ID: Intel CougarPoint HDMI - 0x80860101, // Subsystem ID - 0x00000004, // Number of jacks - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ - AZALIA_SUBVENDOR(0x0, 0x80860101), - - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/intel/cougar_canyon2/mainboard.c b/src/mainboard/intel/cougar_canyon2/mainboard.c deleted file mode 100644 index 07c39e013f..0000000000 --- a/src/mainboard/intel/cougar_canyon2/mainboard.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <drivers/intel/gma/int15.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/fsp_bd82x6x/pch.h> - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -void mainboard_suspend_resume(void) -{ - /* Call SMM finalize() handlers before resume */ - outb(0xcb, 0xb2); -} -#endif - - - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(struct device *dev) -{ - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/intel/cougar_canyon2/mainboard_smi.c b/src/mainboard/intel/cougar_canyon2/mainboard_smi.c deleted file mode 100644 index 5edcf13715..0000000000 --- a/src/mainboard/intel/cougar_canyon2/mainboard_smi.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/fsp_bd82x6x/nvs.h> -#include <southbridge/intel/fsp_bd82x6x/pch.h> -#include <southbridge/intel/fsp_bd82x6x/me.h> -#include <northbridge/intel/fsp_sandybridge/sandybridge.h> -#include <cpu/intel/fsp_model_206ax/model_206ax.h> - -/* - * Change LED_POWER# (SIO GPIO 45) state based on sleep type. - * The IO address is hardcoded as we don't have device path in SMM. - */ -#define SIO_GPIO_BASE_SET4 (0x730 + 3) -#define SIO_GPIO_BLINK_GPIO45 0x25 -void mainboard_smi_sleep(u8 slp_typ) -{ - u8 reg8; - - switch (slp_typ) { - case ACPI_S3: - case ACPI_S4: - break; - - case ACPI_S5: - /* Turn off LED */ - reg8 = inb(SIO_GPIO_BASE_SET4); - reg8 |= (1 << 5); - outb(reg8, SIO_GPIO_BASE_SET4); - break; - } -} - - -static int mainboard_finalized = 0; - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_me_finalize_smm(); - intel_pch_finalize_smm(); - intel_sandybridge_finalize_smm(); - intel_model_206ax_finalize_smm(); - - mainboard_finalized = 1; - break; - } - return 0; -} diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c deleted file mode 100644 index 3813aefa99..0000000000 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ /dev/null @@ -1,311 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <lib.h> -#include <timestamp.h> -#include <arch/io.h> -#include <cf9_reset.h> -#include <device/pci_def.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <cbmem.h> -#include <console/console.h> -#include <halt.h> -#include <program_loading.h> -#include <superio/smsc/sio1007/chip.h> -#include <fsp_util.h> -#include <northbridge/intel/fsp_sandybridge/northbridge.h> -#include <northbridge/intel/fsp_sandybridge/raminit.h> -#include <southbridge/intel/fsp_bd82x6x/pch.h> -#include <southbridge/intel/fsp_bd82x6x/gpio.h> -#include <southbridge/intel/fsp_bd82x6x/me.h> -#include "gpio.h" - -#define SIO_PORT 0x164e - -static void pch_enable_lpc(void) -{ - pci_devfn_t dev = PCH_LPC_DEV; - - /* Set COM1/COM2 decode range */ - pci_write_config16(dev, LPC_IO_DEC, 0x0010); - - /* Enable SuperIO + PS/2 Keyboard/Mouse */ - u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN; - pci_write_config16(dev, LPC_EN, lpc_config); - - /* Map 256 bytes at 0x1600 to the LPC bus. */ - pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601); - - /* Map a range for the runtime registers to the LPC bus. */ - pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); - - if (sio1007_enable_uart_at(SIO_PORT)) { - pci_write_config16(dev, LPC_EN, - lpc_config | COMA_LPC_EN); - } -} - -static void setup_sio_gpios(void) -{ - const u16 port = SIO_PORT; - const u16 runtime_port = 0x180; - - /* Turn on configuration mode. */ - outb(0x55, port); - - /* Set the GPIO direction, polarity, and type. */ - sio1007_setreg(port, 0x31, 1 << 0, 1 << 0); - sio1007_setreg(port, 0x32, 0 << 0, 1 << 0); - sio1007_setreg(port, 0x33, 0 << 0, 1 << 0); - - /* Set the base address for the runtime register block. */ - sio1007_setreg(port, 0x30, runtime_port >> 4, 0xff); - sio1007_setreg(port, 0x21, runtime_port >> 12, 0xff); - - /* Turn on address decoding for it. */ - sio1007_setreg(port, 0x3a, 1 << 1, 1 << 1); - - /* - * Enable the RS232 transiver. - * Set the value of GPIO 10 by changing GP1, bit 0. - */ - u8 byte; - byte = inb(runtime_port + 0xc); - byte |= (1 << 0); - outb(byte, runtime_port + 0xc); - - /* Turn off address decoding for it. */ - sio1007_setreg(port, 0x3a, 0 << 1, 1 << 1); - - /* Turn off configuration mode. */ - outb(0xaa, port); -} - -static void rcba_config(void) -{ - u32 reg32; - - /* - * GFX INTA -> PIRQA (MSI) - * D31IP_SIP SATA INTB -> PIRQD - * D31IP_SMIP SMBUS INTC -> PIRQC - * D31IP_SIP SATA2 INTB -> PIRQD - * D31IP_TTIP THRT INTC -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D28IP_P1IP INTA -> PIRQD - * D28IP_P2IP INTB -> PIRQC - * D28IP_P3IP INTC -> PIRQB - * D28IP_P4IP INTD -> PIRQA - * D28IP_P5IP INTA -> PIRQD - * D28IP_P6IP INTB -> PIRQC - * D28IP_P7IP INTC -> PIRQB - * D28IP_P8IP INTD -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQD (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (INTB << D31IP_SIP2) | - (INTC << D31IP_SMIP) | (INTB << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTD << D28IP_P8IP) | (INTC << D28IP_P7IP) | - (INTB << D28IP_P6IP) | (INTA << D28IP_P5IP) | - (INTD << D28IP_P4IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P2IP) | (INTA << D28IP_P1IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (INTA << D25IP_LIP); - RCBA32(D22IP) = (INTB << D22IP_KTIP) | (INTC << D22IP_IDERIP) | - (INTB << D22IP_MEI2IP) | (INTA << D22IP_MEI1IP); - RCBA32(D20IP) = (INTA << D20IP_XHCIIP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA); - DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC); - DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D26IR, PIRQF, PIRQA, PIRQC, PIRQD); - DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB); - DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - reg32 |= PCH_DISABLE_ALWAYS; - RCBA32(FD) = reg32; -} - -void main(FSP_INFO_HEADER *fsp_info_header) -{ -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) - int boot_mode = 0; -#endif - u32 pm1_cnt; - u16 pm1_sts; - - post_code(0x40); - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&gpio_map); - setup_sio_gpios(); - - console_init(); - post_code(0x41); - - post_code(0x42); - sandybridge_sb_early_initialization(); - - post_code(0x43); - sandybridge_early_initialization(SANDYBRIDGE_MOBILE); - printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - - post_code(0x44); - /* Wait for ME to be ready */ - intel_early_me_status(); - intel_early_me_init(); - intel_early_me_uma_size(); - - post_code(0x45); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - post_code(0x46); - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif - } - - post_code(0x48); - - timestamp_add_now(TS_BEFORE_INITRAM); - - /* - * Call early init to initialize memory and chipset. This function returns - * to the romstage_main_continue function with a pointer to the HOB - * structure. - */ - printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); - fsp_early_init(fsp_info_header); - die("Uh Oh! fsp_early_init should not return here.\n"); -} - -/******************************************************************************* - * The FSP early_init function returns to this function. - * Memory is setup and the stack is set by the FSP. - ******************************************************************************/ -void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { - int cbmem_was_initted; - u32 reg32; - void *cbmem_hob_ptr; - - timestamp_add_now(TS_AFTER_INITRAM); - - /* - * HD AUDIO is not used on this system, so we're using some registers - * in there as temporary registers to save TSC values. This is complete - * now, so disable the audio block. - */ - reg32 = RCBA32(FD); - reg32 |= PCH_DISABLE_HD_AUDIO; - RCBA32(FD) = reg32; - - post_code(0x49); - -#if IS_ENABLED(CONFIG_USBDEBUG) - /* FSP reconfigures USB, so reinit it to have debug */ - early_usbdebug_init(); -#endif - - /* For reference print FSP version */ - u32 version = MCHBAR32(0x5034); - printk(BIOS_DEBUG, "FSP Version %d.%d.%d Build %d\n", - version >> 24, (version >> 16) & 0xff, - (version >> 8) & 0xff, version & 0xff); - printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); - - intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); - - printk(BIOS_SPEW, "FD & FD2 Settings:\n"); - display_fd_settings(); - - report_memory_config(); - - post_code(0x4b); - - early_pch_init(); - post_code(0x4c); - - rcba_config(); - post_code(0x4d); - - quick_ram_check(); - post_code(0x4e); - - cbmem_was_initted = !cbmem_recovery(0); - - if(cbmem_was_initted) { - system_reset(); - } - - /* Save the HOB pointer in CBMEM to be used in ramstage. */ - cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*HobListPtr)); - if (cbmem_hob_ptr == NULL) - die("Could not allocate cbmem for HOB pointer"); - *(u32*)cbmem_hob_ptr = (u32)HobListPtr; - post_code(0x4f); - - /* Load the ramstage. */ - run_ramstage(); - while (1); -} - -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - /* No overrides needed */ - return; -} - -uint64_t get_initial_timestamp(void) -{ - return (uint64_t) pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 4; -} diff --git a/src/mainboard/intel/cougar_canyon2/thermal.h b/src/mainboard/intel/cougar_canyon2/thermal.h deleted file mode 100644 index 17b34c6274..0000000000 --- a/src/mainboard/intel/cougar_canyon2/thermal.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 - -/* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 48 -#define FAN3_THRESHOLD_ON 55 -#define FAN3_PWM 0x40 - -/* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 52 -#define FAN2_THRESHOLD_ON 64 -#define FAN2_PWM 0x80 - -/* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 60 -#define FAN1_THRESHOLD_ON 68 -#define FAN1_PWM 0xb0 - -/* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 66 -#define FAN0_THRESHOLD_ON 78 -#define FAN0_PWM 0xff - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 105 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 91 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 - -#endif diff --git a/src/mainboard/intel/stargo2/Kconfig b/src/mainboard/intel/stargo2/Kconfig deleted file mode 100644 index c152502c7b..0000000000 --- a/src/mainboard/intel/stargo2/Kconfig +++ /dev/null @@ -1,42 +0,0 @@ -if BOARD_INTEL_STARGO2 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_BGA1284 - select NORTHBRIDGE_INTEL_FSP_IVYBRIDGE - select SOUTHBRIDGE_INTEL_FSP_I89XX - select BOARD_ROMSIZE_KB_4096 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select SUPERIO_WINBOND_WPCD376I - select SUPERIO_INTEL_I8900 - select SERIRQ_CONTINUOUS_MODE - select ENABLE_VMX - -config MAINBOARD_DIR - string - default intel/stargo2 - -config MAINBOARD_PART_NUMBER - string - default "Stargo2" - -config MMCONF_BASE_ADDRESS - hex - default 0xf8000000 - -config IRQ_SLOT_COUNT - int - default 18 - -config MAX_CPUS - int - default 16 - - -config VGA_BIOS - bool - default n - - -endif # BOARD_INTEL_STARGO2 diff --git a/src/mainboard/intel/stargo2/Kconfig.name b/src/mainboard/intel/stargo2/Kconfig.name deleted file mode 100644 index a51cff04bb..0000000000 --- a/src/mainboard/intel/stargo2/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_STARGO2 - bool "Stargo2" diff --git a/src/mainboard/intel/stargo2/acpi/ec.asl b/src/mainboard/intel/stargo2/acpi/ec.asl deleted file mode 100644 index b2fed9af98..0000000000 --- a/src/mainboard/intel/stargo2/acpi/ec.asl +++ /dev/null @@ -1,9 +0,0 @@ -/* Dummy file - No license required. */ - -/* - * ec.asl - * - * This file is included by lpc.asl in the southbridge directory. - * It is intended to be used to include any embedded controller - * specific ASL. - */ diff --git a/src/mainboard/intel/stargo2/acpi/hostbridge_pci_irqs.asl b/src/mainboard/intel/stargo2/acpi/hostbridge_pci_irqs.asl deleted file mode 100644 index 829dd7ccf4..0000000000 --- a/src/mainboard/intel/stargo2/acpi/hostbridge_pci_irqs.asl +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 19 }, - - // Network 0:19.0 - Package() { 0x0019ffff, 0, 0, 20 }, - - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 }, - - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - - /* MEI */ - Package() { 0x0016ffff, 0, 0, 16 }, - Package() { 0x0016ffff, 1, 0, 17 }, - - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 23 }, - - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 16 }, - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 2, 0, 18 }, - Package() { 0x001fffff, 3, 0, 16 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - - // EHCI #2 0:19.0 - Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - - /* Management Engine Interface */ - Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/intel/stargo2/acpi/mainboard.asl b/src/mainboard/intel/stargo2/acpi/mainboard.asl deleted file mode 100644 index edd592ae87..0000000000 --- a/src/mainboard/intel/stargo2/acpi/mainboard.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Power Button */ -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) - - // Wake - Name(_PRW, Package(){0x1d, 0x05}) -} diff --git a/src/mainboard/intel/stargo2/acpi/platform.asl b/src/mainboard/intel/stargo2/acpi/platform.asl deleted file mode 100644 index be23b43e81..0000000000 --- a/src/mainboard/intel/stargo2/acpi/platform.asl +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ - /* NVS has a flag to determine USB policy in S3 */ - if (S3U0) { - Store (One, GP47) // Enable USB0 - } Else { - Store (Zero, GP47) // Disable USB0 - } - - /* NVS has a flag to determine USB policy in S3 */ - if (S3U1) { - Store (One, GP56) // Enable USB1 - } Else { - Store (Zero, GP56) // Disable USB1 - } -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/intel/stargo2/acpi/superio.asl b/src/mainboard/intel/stargo2/acpi/superio.asl deleted file mode 100644 index e69de29bb2..0000000000 --- a/src/mainboard/intel/stargo2/acpi/superio.asl +++ /dev/null diff --git a/src/mainboard/intel/stargo2/acpi_tables.c b/src/mainboard/intel/stargo2/acpi_tables.c deleted file mode 100644 index 2cc7eb5ae6..0000000000 --- a/src/mainboard/intel/stargo2/acpi_tables.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -#include <southbridge/intel/fsp_i89xx/pch.h> -#include <southbridge/intel/fsp_i89xx/nvs.h> -#include "thermal.h" - -static global_nvs_t *gnvs_; - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - gnvs_ = gnvs; - memset((void *)gnvs, 0, sizeof(*gnvs)); - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 0; - gnvs->s3u1 = 0; - - /* - * Enable USB ports in S5 by default - * to be consistent with back port behavior - */ - gnvs->s5u0 = 1; - gnvs->s5u1 = 1; - - acpi_update_thermal_table(gnvs); -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/mainboard/intel/stargo2/board_info.txt b/src/mainboard/intel/stargo2/board_info.txt deleted file mode 100644 index b89835dfc8..0000000000 --- a/src/mainboard/intel/stargo2/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: eval -Release year: 2010 diff --git a/src/mainboard/intel/stargo2/cmos.layout b/src/mainboard/intel/stargo2/cmos.layout deleted file mode 100644 index 8d4b282275..0000000000 --- a/src/mainboard/intel/stargo2/cmos.layout +++ /dev/null @@ -1,104 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/intel/stargo2/devicetree.cb b/src/mainboard/intel/stargo2/devicetree.cb deleted file mode 100644 index 5cf8384ec1..0000000000 --- a/src/mainboard/intel/stargo2/devicetree.cb +++ /dev/null @@ -1,97 +0,0 @@ -chip northbridge/intel/fsp_sandybridge - - device cpu_cluster 0 on - chip cpu/intel/socket_BGA1284 - device lapic 0 on end - end - chip cpu/intel/fsp_model_206ax - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 01.0 on end # host bridge (slot 2 - black x16 slot (only x8)) - device pci 01.1 on end # host bridge (PCIe Ethernet controllers) - device pci 01.2 off end # host bridge (off - no additional bifurcation) - device pci 02.0 off end # vga controller - device pci 06.0 on end # host bridge (slot 1 - blue x4 slot) - - chip southbridge/intel/fsp_i89xx # Intel Series 89xx Cave Creek PCH - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x01" - register "sata_port_map" = "0x30" - register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" - - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 1c.0 on end # PCIe Port #1 (Slot #3 - x1) - device pci 1c.1 on end # PCIe Port #2 (Slot #4 - x1) - device pci 1c.2 on end # PCIe Port #3 (Slot #5 - x1) - device pci 1c.3 on end # PCIe Port #4 (Slot #6 - x1) - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1f.0 on # LPC bridge - - # The top serial port is controlled by jumper - # J3a3. If the jumper is off, the serial - # port connector is routed to the SIO. If - # the jumper is on, the connector goes to - # the PCH's serial port. There is no way - # to tell in software which it's connected - # to. - - chip superio/intel/i8900 - device pnp 4e.4 on # Com3 - io 0x60 = 0x3E8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.6 on # Watchdog Timer - io 0x60 = 0x600 - irq 0x70 = 7 - end - end - - chip superio/winbond/wpcd376i - device pnp 2e.0 off end # FDC - device pnp 2e.1 off end # LPT - device pnp 2e.2 off end # IR - device pnp 2e.3 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # System wakeup - device pnp 2e.5 on # PS/2 mouse - irq 0x70 = 0x0C - end - device pnp 2e.6 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 0x01 - end - device pnp 2e.7 off end # GPIO - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal - device pci 1f.7 on end # WDT - end - end -end diff --git a/src/mainboard/intel/stargo2/dsdt.asl b/src/mainboard/intel/stargo2/dsdt.asl deleted file mode 100644 index b4ae0ec4b6..0000000000 --- a/src/mainboard/intel/stargo2/dsdt.asl +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - #include <southbridge/intel/fsp_i89xx/acpi/platform.asl> - - // Some generic macros - #include "acpi/platform.asl" - - // global NVS and variables - #include <southbridge/intel/fsp_i89xx/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - #include <cpu/intel/fsp_model_206ax/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl> - #include <southbridge/intel/fsp_i89xx/acpi/pch.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - } - - /* Chipset specific sleep states */ - #include <southbridge/intel/fsp_i89xx/acpi/sleepstates.asl> -} diff --git a/src/mainboard/intel/stargo2/gpio.h b/src/mainboard/intel/stargo2/gpio.h deleted file mode 100644 index 675580b10a..0000000000 --- a/src/mainboard/intel/stargo2/gpio.h +++ /dev/null @@ -1,303 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include <southbridge/intel/fsp_i89xx/gpio.h> - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - - /* 1. The following bits are always 1 because they are always - * unMultiplexed: 0, 8, 15, 24, 27, and 28. - */ - - /* - * GPIO 17 - * This strap along with the fuse setting determines DMI TX - * voltage level and TX/RX termination. - * PU - SNB GLD (J1G7 Open) - * PD - IVB GLD (J1G7 Jumpered) - * - * GPIO 25 - Output - * Low = 1.35V DDR3 - * High = 1.5V DDR3 - * - * 1.35V DDR3 is Forced by J9C2 Jumpered - * 1.35V / 1.5V switching by GPIO 25 if J9C2 is open - * - * GPIO 30 - Core OSC power strap - * Low SFR OUT (INT) J1J1 Jumpered (Default) - * High VCCP1P0_STBY (EXT) J1J1 Open - */ - - .gpio0 = GPIO_MODE_NONE, /* Unused */ - .gpio1 = GPIO_MODE_NONE, /* Unused */ - .gpio2 = GPIO_MODE_NONE, /* Unused */ - .gpio3 = GPIO_MODE_NONE, /* Unused */ - .gpio4 = GPIO_MODE_NONE, /* Unused */ - .gpio5 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO3 - MLR TODO: What does this do? */ - .gpio6 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO4 - MLR TODO: What does this do? */ - .gpio7 = GPIO_MODE_NONE, /* Unused */ - .gpio8 = GPIO_MODE_NONE, /* Unused */ - .gpio9 = GPIO_MODE_NONE, /* Unused */ - .gpio10 = GPIO_MODE_NONE, /* Unused */ - .gpio11 = GPIO_MODE_NONE, /* Unused */ - .gpio12 = GPIO_MODE_NONE, /* Unused */ - .gpio13 = GPIO_MODE_NONE, /* Unused */ - .gpio14 = GPIO_MODE_NONE, /* Unused */ - .gpio15 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO0_SUS - MLR TODO*/ - .gpio16 = GPIO_MODE_NONE, /* Unused */ - .gpio17 = GPIO_MODE_GPIO, /* PCH_TACH0_GP17 Note:- TODO: What register does this?*/ - .gpio18 = GPIO_MODE_NONE, /* Unused */ - .gpio19 = GPIO_MODE_NONE, /* Unused */ - .gpio20 = GPIO_MODE_NONE, /* Unused */ - .gpio21 = GPIO_MODE_NONE, /* Unused */ - .gpio22 = GPIO_MODE_NONE, /* Unused */ - .gpio23 = GPIO_MODE_NONE, /* Unused */ - .gpio24 = GPIO_MODE_NONE, /* Unused */ - .gpio25 = GPIO_MODE_GPIO, /* VDD1P5_DDR OUTPUT LEVEL - MLR TODO: Config for this? Detect memory? */ - .gpio26 = GPIO_MODE_GPIO, /* SIO_PME_N - MLR TODO: Configure this */ - .gpio27 = GPIO_MODE_GPIO, /* FP_LED_YLW_N - MLR TODO: Configure this */ - .gpio28 = GPIO_MODE_NONE, /* Unused */ - .gpio29 = GPIO_MODE_NONE, /* NA */ - .gpio30 = GPIO_MODE_GPIO, /* PCH_SUS_PWR_ACK_GP30 - MLR TODO */ - .gpio31 = GPIO_MODE_NONE, /* Unused */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, /* Unused */ - .gpio1 = GPIO_DIR_INPUT, /* Unused */ - .gpio2 = GPIO_DIR_INPUT, /* Unused */ - .gpio3 = GPIO_DIR_INPUT, /* Unused */ - .gpio4 = GPIO_DIR_INPUT, /* Unused */ - .gpio5 = GPIO_DIR_OUTPUT, /* GPIO */ - .gpio6 = GPIO_DIR_OUTPUT, /* GPIO */ - .gpio7 = GPIO_DIR_INPUT, /* Unused */ - .gpio8 = GPIO_DIR_INPUT, /* Unused */ - .gpio9 = GPIO_DIR_INPUT, /* Unused */ - .gpio10 = GPIO_DIR_INPUT, /* Unused */ - .gpio11 = GPIO_DIR_INPUT, /* Unused */ - .gpio12 = GPIO_DIR_INPUT, /* Unused */ - .gpio13 = GPIO_DIR_INPUT, /* Unused */ - .gpio14 = GPIO_DIR_INPUT, /* Unused */ - .gpio15 = GPIO_DIR_OUTPUT, /* GPIO */ - .gpio16 = GPIO_DIR_INPUT, /* Unused */ - .gpio17 = GPIO_DIR_INPUT, /* GPIO */ - .gpio18 = GPIO_DIR_INPUT, /* Unused */ - .gpio19 = GPIO_DIR_INPUT, /* Unused */ - .gpio20 = GPIO_DIR_INPUT, /* Unused */ - .gpio21 = GPIO_DIR_INPUT, /* Unused */ - .gpio22 = GPIO_DIR_INPUT, /* Unused */ - .gpio23 = GPIO_DIR_INPUT, /* Unused */ - .gpio24 = GPIO_DIR_INPUT, /* Unused */ - .gpio25 = GPIO_DIR_OUTPUT, /* GPIO */ - .gpio26 = GPIO_DIR_INPUT, /* GPIO */ - .gpio27 = GPIO_DIR_OUTPUT, /* GPIO */ - .gpio28 = GPIO_DIR_INPUT, /* Unused */ - .gpio29 = GPIO_DIR_INPUT, /* NA */ - .gpio30 = GPIO_DIR_OUTPUT, /* GPIO */ - .gpio31 = GPIO_DIR_INPUT, /* Unused */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio1 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio2 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio3 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio4 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio5 = GPIO_LEVEL_LOW, /* GPIO Out */ - .gpio6 = GPIO_LEVEL_LOW, /* GPIO Out */ - .gpio7 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio8 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio9 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio10 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio11 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio12 = GPIO_LEVEL_LOW, /* Unused */ - .gpio13 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio14 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio15 = GPIO_LEVEL_LOW, /* GPIO Out */ - .gpio16 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio17 = GPIO_LEVEL_HIGH, /* GPIO In */ - .gpio18 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio19 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio20 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio21 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio22 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio23 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio24 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio25 = GPIO_LEVEL_HIGH, /* GPIO Out */ - .gpio26 = GPIO_LEVEL_HIGH, /* GPIO In */ - .gpio27 = GPIO_LEVEL_LOW, /* GPIO Out */ - .gpio28 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio29 = GPIO_LEVEL_HIGH, /* NA */ - .gpio30 = GPIO_LEVEL_LOW, /* GPIO Out */ - .gpio31 = GPIO_LEVEL_HIGH, /* Unused */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - /* - * Gpio 46: Bios Recovery strap - * High = Normal mode - J5A3 (Open) - * Low = Recovery Mode - J5A3 (Jumpered) - */ - .gpio32 = GPIO_MODE_GPIO, /* PCH_CLKRUN_N - MLR TODO:*/ - .gpio33 = GPIO_MODE_NONE, /* Unused (SECURITY OVERRIDE STRAP (J1G4)) */ - .gpio34 = GPIO_MODE_NONE, /* Unused*/ - .gpio35 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO2 : MLR TODO*/ - .gpio36 = GPIO_MODE_NONE, /* Unused */ - .gpio37 = GPIO_MODE_NONE, /* Unused */ - .gpio38 = GPIO_MODE_GPIO, /* Dev Kit Board Version high bit */ - .gpio39 = GPIO_MODE_GPIO, /* Dev Kit Board Version low bit */ - .gpio40 = GPIO_MODE_NATIVE, /* PCH_GP40_OC_N<1> */ - .gpio41 = GPIO_MODE_NATIVE, /* PCH_GP41_OC_N<2> */ - .gpio42 = GPIO_MODE_NATIVE, /* PCH_GP42_OC_N<3> */ - .gpio43 = GPIO_MODE_NONE, /* Unused */ - .gpio44 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO1_SUS : MLR TODO */ - .gpio45 = GPIO_MODE_NONE, /* Unused */ - .gpio46 = GPIO_MODE_GPIO, /* BIOS RECOVERY STRAP - Note : MLR TODO */ - .gpio47 = GPIO_MODE_NONE, /* Unused */ - .gpio48 = GPIO_MODE_NONE, /* Unused */ - .gpio49 = GPIO_MODE_NONE, /* Unused (TEMP_ALERT# J2H2 test jumper) */ - .gpio50 = GPIO_MODE_NONE, /* Unused */ - .gpio51 = GPIO_MODE_NONE, /* Unused */ - .gpio52 = GPIO_MODE_NONE, /* Unused */ - .gpio53 = GPIO_MODE_NONE, /* Unused */ - .gpio54 = GPIO_MODE_NONE, /* Unused */ - .gpio55 = GPIO_MODE_NONE, /* Unused */ - .gpio56 = GPIO_MODE_GPIO, /* CONN_GBE_RESET_N */ - .gpio57 = GPIO_MODE_NONE, /* Unused */ - .gpio58 = GPIO_MODE_NATIVE, /* PCH_SML1_CLK */ - .gpio59 = GPIO_MODE_NATIVE, /* PCH_GP59_OC_N<0> */ - .gpio60 = GPIO_MODE_NONE, /* Unused */ - .gpio61 = GPIO_MODE_NATIVE, /* PCH_SUS_STAT_N */ - .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK */ - .gpio63 = GPIO_MODE_NATIVE, /* PCH_SLP_S5_N */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_OUTPUT, /* GPIO Out */ - .gpio33 = GPIO_DIR_INPUT, /* Unused */ - .gpio34 = GPIO_DIR_INPUT, /* Unused */ - .gpio35 = GPIO_DIR_OUTPUT, /* GPIO Out */ - .gpio36 = GPIO_DIR_INPUT, /* Unused */ - .gpio37 = GPIO_DIR_INPUT, /* Unused */ - .gpio38 = GPIO_DIR_INPUT, /* GPIO In */ - .gpio39 = GPIO_DIR_INPUT, /* GPIO In */ - .gpio40 = GPIO_DIR_INPUT, /* Native */ - .gpio41 = GPIO_DIR_INPUT, /* Native */ - .gpio42 = GPIO_DIR_INPUT, /* Native */ - .gpio43 = GPIO_DIR_INPUT, /* Unused */ - .gpio44 = GPIO_DIR_OUTPUT, /* GPIO Out */ - .gpio45 = GPIO_DIR_INPUT, /* Unused */ - .gpio46 = GPIO_DIR_INPUT, /* GPIO In */ - .gpio47 = GPIO_DIR_INPUT, /* Unused */ - .gpio48 = GPIO_DIR_INPUT, /* Unused */ - .gpio49 = GPIO_DIR_INPUT, /* Unused */ - .gpio50 = GPIO_DIR_INPUT, /* Unused */ - .gpio51 = GPIO_DIR_INPUT, /* Unused */ - .gpio52 = GPIO_DIR_INPUT, /* Unused */ - .gpio53 = GPIO_DIR_INPUT, /* Unused */ - .gpio54 = GPIO_DIR_INPUT, /* Unused */ - .gpio55 = GPIO_DIR_INPUT, /* Unused */ - .gpio56 = GPIO_DIR_OUTPUT, /* GPIO Out */ - .gpio57 = GPIO_DIR_INPUT, /* Unused */ - .gpio58 = GPIO_DIR_INPUT, /* Native */ - .gpio59 = GPIO_DIR_INPUT, /* Native */ - .gpio60 = GPIO_DIR_INPUT, /* Unused */ - .gpio61 = GPIO_DIR_INPUT, /* Native */ - .gpio62 = GPIO_DIR_INPUT, /* Native */ - .gpio63 = GPIO_DIR_INPUT, /* Native */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, /* GPIO Out */ - .gpio33 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio34 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio35 = GPIO_LEVEL_LOW, /* GPIO Out */ - .gpio36 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio37 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio38 = GPIO_LEVEL_HIGH, /* GPIO In */ - .gpio39 = GPIO_LEVEL_HIGH, /* GPIO In */ - .gpio40 = GPIO_LEVEL_HIGH, /* Native */ - .gpio41 = GPIO_LEVEL_HIGH, /* Native */ - .gpio42 = GPIO_LEVEL_HIGH, /* Native */ - .gpio43 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio44 = GPIO_LEVEL_LOW, /* GPIO Out */ - .gpio45 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio46 = GPIO_LEVEL_HIGH, /* GPIO In */ - .gpio47 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio48 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio49 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio50 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio51 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio52 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio53 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio54 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio55 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio56 = GPIO_LEVEL_LOW, /* GPIO Out */ - .gpio57 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio58 = GPIO_LEVEL_HIGH, /* Native */ - .gpio59 = GPIO_LEVEL_HIGH, /* Native */ - .gpio60 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio61 = GPIO_LEVEL_HIGH, /* Native */ - .gpio62 = GPIO_LEVEL_HIGH, /* Native */ - .gpio63 = GPIO_LEVEL_HIGH, /* Native */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio72 = GPIO_MODE_NONE, /* Unused */ - .gpio73 = GPIO_MODE_NONE, /* Unused */ - .gpio74 = GPIO_MODE_NATIVE, /* PCH_SML1ALERT */ - .gpio75 = GPIO_MODE_NATIVE, /* PCH_SML1_DAT */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio72 = GPIO_DIR_INPUT, /* Unused */ - .gpio73 = GPIO_DIR_INPUT, /* Unused */ - .gpio74 = GPIO_DIR_INPUT, /* Native */ - .gpio75 = GPIO_DIR_INPUT, /* Native */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio72 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio73 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio74 = GPIO_LEVEL_HIGH, /* Native */ - .gpio75 = GPIO_LEVEL_HIGH, /* Native */ -}; - -const struct pch_gpio_map gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/intel/stargo2/mainboard.c b/src/mainboard/intel/stargo2/mainboard.c deleted file mode 100644 index c2b5d7d648..0000000000 --- a/src/mainboard/intel/stargo2/mainboard.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/fsp_i89xx/pch.h> - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -void mainboard_suspend_resume(void) -{ - /* Call SMM finalize() handlers before resume */ - outb(0xcb, 0xb2); -} -#endif - - - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(struct device *dev) -{ -} - - - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/intel/stargo2/mainboard_smi.c b/src/mainboard/intel/stargo2/mainboard_smi.c deleted file mode 100644 index 0e7e986c20..0000000000 --- a/src/mainboard/intel/stargo2/mainboard_smi.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/fsp_i89xx/nvs.h> -#include <southbridge/intel/fsp_i89xx/pch.h> -#include <southbridge/intel/fsp_i89xx/me.h> -#include <northbridge/intel/fsp_sandybridge/sandybridge.h> -#include <cpu/intel/fsp_model_206ax/model_206ax.h> - -void mainboard_smi_sleep(u8 slp_typ) -{ - u8 reg8; - - switch (slp_typ) { - case ACPI_S3: - case ACPI_S4: - case ACPI_S5: - break; - } -} - - -static int mainboard_finalized = 0; - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_me_finalize_smm(); - intel_pch_finalize_smm(); - intel_sandybridge_finalize_smm(); - intel_model_206ax_finalize_smm(); - - mainboard_finalized = 1; - break; - } - return 0; -} diff --git a/src/mainboard/intel/stargo2/romstage.c b/src/mainboard/intel/stargo2/romstage.c deleted file mode 100644 index 56f0fc0b4f..0000000000 --- a/src/mainboard/intel/stargo2/romstage.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <timestamp.h> -#include <arch/io.h> -#include <device/pci_def.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <halt.h> -#include <reset.h> -#include <fsp_util.h> -#include <northbridge/intel/fsp_sandybridge/northbridge.h> -#include <northbridge/intel/fsp_sandybridge/raminit.h> -#include <southbridge/intel/fsp_i89xx/pch.h> -#include <southbridge/intel/fsp_i89xx/gpio.h> -#include <southbridge/intel/fsp_i89xx/me.h> -#include <southbridge/intel/fsp_i89xx/romstage.h> -#include <superio/winbond/wpcd376i/wpcd376i.h> -#include <superio/intel/i8900/i8900.h> -#include "gpio.h" - -#define SIO_PORT 0x2e -#define SERIAL_DEV PNP_DEV(SIO_PORT, 0x03) -#define WDT_DEV PNP_DEV(SIO_PORT, 0x06) -#define WDT_BASE_ADDR 0x600 - -/* - * Get function disables - any changes here should match in devicetree - * @param fd_mask - * @param fd2_mask - */ -void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) -{ - *fd_mask |= PCH_DISABLE_ALWAYS; -} - -/** - * Get LPC setting - enables various devices (KB, mouse, etc.) - */ -uint16_t get_lpc_setting(void) -{ - /* Enable SuperIO (2E/4E) + COM1 & Keyboard controller */ - return CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN; -} - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry(void) -{ - /* Early SuperIO setup - Using SIO Serial Port*/ - wpcd376i_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - i8900_enable_wdt(WDT_DEV, WDT_BASE_ADDR); -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry(void) -{ - -} - -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - /* No overrides needed */ - return; -} diff --git a/src/mainboard/intel/stargo2/thermal.h b/src/mainboard/intel/stargo2/thermal.h deleted file mode 100644 index 609f3465e8..0000000000 --- a/src/mainboard/intel/stargo2/thermal.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 - -/* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 48 -#define FAN3_THRESHOLD_ON 55 -#define FAN3_PWM 0x40 - -/* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 52 -#define FAN2_THRESHOLD_ON 64 -#define FAN2_PWM 0x80 - -/* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 60 -#define FAN1_THRESHOLD_ON 68 -#define FAN1_PWM 0xb0 - -/* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 66 -#define FAN0_THRESHOLD_ON 78 -#define FAN0_PWM 0xff - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 - -#endif |