4 files changed, 95 insertions, 3 deletions
diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
index ee6406049c..31aa3d8723 100644
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -11,15 +11,16 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_2048 if !VBOOT
 	select BOARD_ROMSIZE_KB_16384 if VBOOT
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
-	select MAINBOARD_FORCE_NATIVE_VGA_INIT
+	select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS
 	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_CHROMEOS
 
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_BOOTBLOCK
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_VBNV_CMOS
-	select VBOOT_NO_BOARD_SUPPORT
+	select VBOOT_NO_BOARD_SUPPORT if !CHROMEOS
 	select GBB_FLAG_DISABLE_LID_SHUTDOWN
 	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
 	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
@@ -27,7 +28,8 @@ config VBOOT
 
 config FMDFILE
 	string
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwab-16M.fmd" if VBOOT_SLOTS_RW_AB
 
 if VBOOT
 
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc
index 133a213cc6..e142d4d5c1 100644
--- a/src/mainboard/emulation/qemu-q35/Makefile.inc
+++ b/src/mainboard/emulation/qemu-q35/Makefile.inc
@@ -10,3 +10,7 @@ postcar-y += ../qemu-i440fx/exit_car.S
 ramstage-y += ../qemu-i440fx/fw_cfg.c
 ramstage-y += ../qemu-i440fx/memmap.c
 ramstage-y += ../qemu-i440fx/northbridge.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c
new file mode 100644
index 0000000000..50e48caf98
--- /dev/null
+++ b/src/mainboard/emulation/qemu-q35/chromeos.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include "../qemu-i440fx/fw_cfg.h"
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, 1, "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{-1, ACTIVE_HIGH, 0, "EC in RW"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+	return 0;
+}
+
+/*
+ * Enable recovery mode with fw_cfg option to qemu:
+ *   -fw_cfg name=opt/cros/recovery,string=1
+ */
+int get_recovery_mode_switch(void)
+{
+	FWCfgFile f;
+
+	if (!fw_cfg_check_file(&f, "opt/cros/recovery")) {
+		uint8_t rec_mode;
+		if (f.size != 1) {
+			printk(BIOS_ERR, "opt/cros/recovery invalid size %d\n", f.size);
+			return 0;
+		}
+		fw_cfg_get(f.select, &rec_mode, f.size);
+		if (rec_mode == '1') {
+			printk(BIOS_INFO, "Recovery is enabled.\n");
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, "QEMU"),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd
new file mode 100644
index 0000000000..fcbfa95b69
--- /dev/null
+++ b/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd
@@ -0,0 +1,28 @@
+FLASH@0xff000000 0x1000000 {
+	SI_BIOS 0x1000000 {
+		RW_SECTION_A 0x1c0000 {
+			VBLOCK_A 0x10000
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 0x40
+		}
+		RW_SECTION_B 0x1c0000 {
+			VBLOCK_B 0x10000
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 0x40
+		}
+		RW_SHARED 0x4000 {
+			SHARED_DATA 0x2000
+			VBLOCK_DEV 0x2000
+		}
+		RW_VPD(PRESERVE) 0x1000
+		RW_LEGACY(CBFS) 0x10000
+		WP_RO {
+			FMAP 0x800
+			RO_FRID 0x40
+			RO_PADDING 0x7c0
+			RO_VPD(PRESERVE) 0x1000
+			GBB 0x1e000
+			COREBOOT(CBFS)
+		}
+	}
+}