8 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index 2d780dbedd..e7e65f2d44 100644
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -79,6 +79,7 @@ static const struct mem_controller ctrl = {
 	.channel0 = { DIMM0 },
 };
 
+#include <cpu/intel/car.h>
 void main(unsigned long bist)
 {
 	/* Enable multifunction for northbridge. */
diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c
index ebe6a503a1..b3b515df2b 100644
--- a/src/mainboard/via/epia-m/romstage.c
+++ b/src/mainboard/via/epia-m/romstage.c
@@ -66,6 +66,7 @@ static void enable_shadow_ram(void)
 	pci_write_config8(dev, 0x63, shadowreg);
 }
 
+#include <cpu/intel/car.h>
 static void main(unsigned long bist)
 {
 	device_t dev;
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 6198cda12d..c33acbe24b 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -373,6 +373,7 @@ static void EmbedComInit(void)
 #endif
 
 /* cache_as_ram.inc jumps to here. */
+#include <cpu/intel/car.h>
 void main(unsigned long bist)
 {
 	u16 boot_mode;
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
index ece64d8597..969e2b6aec 100644
--- a/src/mainboard/via/epia-m850/romstage.c
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -42,6 +42,7 @@
 #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
 
 /* cache_as_ram.inc jumps to here. */
+#include <cpu/intel/car.h>
 void main(unsigned long bist)
 {
 	u32 tolm;
diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c
index 568dab5667..5c1477d3a9 100644
--- a/src/mainboard/via/epia-n/romstage.c
+++ b/src/mainboard/via/epia-n/romstage.c
@@ -101,6 +101,7 @@ static void enable_shadow_ram(void)
 	pci_write_config8(ctrl.d0f3, 0x82, shadowreg);
 }
 
+#include <cpu/intel/car.h>
 static void main(unsigned long bist)
 {
 	unsigned long x;
diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c
index b1e6c54169..e839541a27 100644
--- a/src/mainboard/via/epia/romstage.c
+++ b/src/mainboard/via/epia/romstage.c
@@ -69,6 +69,7 @@ static void enable_shadow_ram(void)
 	pci_write_config8(dev, 0x63, shadowreg);
 }
 
+#include <cpu/intel/car.h>
 static void main(unsigned long bist)
 {
 	if (bist == 0)
diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c
index b2703506a2..aa7e2de6ec 100644
--- a/src/mainboard/via/pc2500e/romstage.c
+++ b/src/mainboard/via/pc2500e/romstage.c
@@ -55,6 +55,7 @@ static const struct mem_controller ctrl = {
 	.channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */
 };
 
+#include <cpu/intel/car.h>
 void main(unsigned long bist)
 {
 	/* Enable multifunction for northbridge. */
diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c
index e1532be14f..d3ad0e2964 100644
--- a/src/mainboard/via/vt8454c/romstage.c
+++ b/src/mainboard/via/vt8454c/romstage.c
@@ -83,6 +83,7 @@ static void enable_shadow_ram(const struct mem_controller *ctrl)
 	pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
 }
 
+#include <cpu/intel/car.h>
 void main(unsigned long bist)
 {
 	/* Set statically so it should work with cx700 as well */