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-rw-r--r--src/mainboard/tyan/s2912/romstage.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 0dd7297ea2..aa6107637d 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -37,7 +37,7 @@
#include <spd.h>
#include <usbdebug.h>
#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@@ -49,7 +49,7 @@
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -77,8 +77,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"