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Diffstat (limited to 'src/mainboard/tyan/s2891/cache_as_ram_auto.c')
-rw-r--r--src/mainboard/tyan/s2891/cache_as_ram_auto.c206
1 files changed, 96 insertions, 110 deletions
diff --git a/src/mainboard/tyan/s2891/cache_as_ram_auto.c b/src/mainboard/tyan/s2891/cache_as_ram_auto.c
index aceffc33fa..78a2bb1ac8 100644
--- a/src/mainboard/tyan/s2891/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2891/cache_as_ram_auto.c
@@ -8,7 +8,6 @@
#define SET_NB_CFG_54 1
#endif
-
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@@ -21,17 +20,6 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -54,7 +42,6 @@ static void post_code(uint8_t value) {
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
static void memreset_setup(void)
{
}
@@ -78,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "sdram/generic_sdram.c"
/* tyan does not want the default */
-#include "resourcemap.c"
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
@@ -92,7 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
-
#if USE_FALLBACK_IMAGE == 1
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
@@ -101,28 +87,28 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
- unsigned value;
- uint32_t dword;
- uint8_t byte;
-
- /* subject decoding*/
- byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-
- /* LPC Positive Decode 0 */
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
- /* Serial 0, Serial 1 */
- dword |= (1<<0) | (1<<1);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-#if 1
- /* s2891 has onboard LPC port 80 */
- /*Hope I can enable port 80 here
- It will decode port 80 to LPC, If you are using PCI post code you can not do this */
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
+ unsigned value;
+ uint32_t dword;
+ uint8_t byte;
+
+ /* subject decoding*/
+ byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
+ byte |= 0x20;
+ pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
+
+ /* LPC Positive Decode 0 */
+ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
+ /* Serial 0, Serial 1 */
+ dword |= (1<<0) | (1<<1);
+ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
+
+#if 1
+ /* s2891 has onboard LPC port 80 */
+ /*Hope I can enable port 80 here
+ It will decode port 80 to LPC, If you are using PCI post code you can not do this */
+ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
+ dword |= (1<<16);
+ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
#endif
@@ -130,48 +116,48 @@ static void sio_setup(void)
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
- unsigned last_boot_normal_x = last_boot_normal();
-
- /* Is this a cpu only reset? or Is this a secondary cpu? */
- if ((cpu_init_detectedx) || (!boot_cpu())) {
- if (last_boot_normal_x) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
-
- enumerate_ht_chain();
-
- sio_setup();
-
- /* Setup the ck804 */
- ck804_enable_rom();
-
- /* Is this a deliberate reset by the bios */
-// post_code(0x22);
- if (bios_reset_detected() && last_boot_normal_x) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
+ unsigned last_boot_normal_x = last_boot_normal();
+
+ /* Is this a cpu only reset? or Is this a secondary cpu? */
+ if ((cpu_init_detectedx) || (!boot_cpu())) {
+ if (last_boot_normal_x) {
+ goto normal_image;
+ } else {
+ goto fallback_image;
+ }
+ }
+
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+
+ enumerate_ht_chain();
+
+ sio_setup();
+
+ /* Setup the ck804 */
+ ck804_enable_rom();
+
+ /* Is this a deliberate reset by the bios */
+// post_code(0x22);
+ if (bios_reset_detected() && last_boot_normal_x) {
+ goto normal_image;
+ }
+ /* This is the primary cpu how should I boot? */
+ else if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
normal_image:
-// post_code(0x23);
- __asm__ volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) , "b" (cpu_init_detectedx)/* inputs */
- );
+// post_code(0x23);
+ __asm__ volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
+ );
fallback_image:
-// post_code(0x25);
+// post_code(0x25);
;
}
#endif
@@ -182,71 +168,71 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if USE_FALLBACK_IMAGE == 1
- failover_process(bist, cpu_init_detectedx);
+ failover_process(bist, cpu_init_detectedx);
#endif
- real_main(bist, cpu_init_detectedx);
+ real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- (0xa<<3)|0, (0xa<<3)|2, 0, 0,
- (0xa<<3)|1, (0xa<<3)|3, 0, 0,
+ (0xa<<3)|0, (0xa<<3)|2, 0, 0,
+ (0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
- (0xa<<3)|4, (0xa<<3)|6, 0, 0,
- (0xa<<3)|5, (0xa<<3)|7, 0, 0,
+ (0xa<<3)|4, (0xa<<3)|6, 0, 0,
+ (0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif
};
- int needs_reset;
- unsigned bsp_apicid = 0;
+ int needs_reset;
+ unsigned bsp_apicid = 0;
- struct mem_controller ctrl[8];
- unsigned nodes;
+ struct mem_controller ctrl[8];
+ unsigned nodes;
- if (bist == 0) {
- bsp_apicid = init_cpus(cpu_init_detectedx);
- }
+ if (bist == 0) {
+ bsp_apicid = init_cpus(cpu_init_detectedx);
+ }
// post_code(0x32);
-
+
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
+ uart_init();
+ console_init();
+
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- setup_s2891_resource_map();
+ setup_s2891_resource_map();
#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
+ dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
- wait_all_core0_started();
+ wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
- // It is said that we should start core1 after all core0 launched
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
+ // It is said that we should start core1 after all core0 launched
+ start_other_cores();
+ wait_all_other_cores_started(bsp_apicid);
#endif
- needs_reset |= ht_setup_chains_x();
+ needs_reset |= ht_setup_chains_x();
- needs_reset |= ck804_early_setup_x();
+ needs_reset |= ck804_early_setup_x();
- if (needs_reset) {
- print_info("ht reset -\r\n");
-// soft_reset();
- }
+ if (needs_reset) {
+ print_info("ht reset -\r\n");
+ // soft_reset();
+ }
- allow_all_aps_stop(bsp_apicid);
+ allow_all_aps_stop(bsp_apicid);
- nodes = get_nodes();
- //It's the time to set ctrl now;
- fill_mem_ctrl(nodes, ctrl, spd_addr);
+ nodes = get_nodes();
+ //It's the time to set ctrl now;
+ fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
#if 0
@@ -260,7 +246,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(nodes, ctrl);
#if 0
- print_pci_devices();
+ print_pci_devices();
#endif
#if 0
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-16 21:03:16 +0000