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-rw-r--r--src/mainboard/system76/gaze15/Kconfig75
-rw-r--r--src/mainboard/system76/gaze15/Kconfig.name2
-rw-r--r--src/mainboard/system76/gaze15/Makefile.inc8
-rw-r--r--src/mainboard/system76/gaze15/acpi/gpe.asl11
-rw-r--r--src/mainboard/system76/gaze15/acpi/mainboard.asl13
-rw-r--r--src/mainboard/system76/gaze15/acpi/sleep.asl11
-rw-r--r--src/mainboard/system76/gaze15/board_info.txt8
-rw-r--r--src/mainboard/system76/gaze15/bootblock.c10
-rw-r--r--src/mainboard/system76/gaze15/data.vbtbin0 -> 6144 bytes
-rw-r--r--src/mainboard/system76/gaze15/devicetree.cb216
-rw-r--r--src/mainboard/system76/gaze15/dsdt.asl31
-rw-r--r--src/mainboard/system76/gaze15/gpio.c277
-rw-r--r--src/mainboard/system76/gaze15/gpio_early.c17
-rw-r--r--src/mainboard/system76/gaze15/hda_verb.c26
-rw-r--r--src/mainboard/system76/gaze15/include/mainboard/gpio.h9
-rw-r--r--src/mainboard/system76/gaze15/ramstage.c13
-rw-r--r--src/mainboard/system76/gaze15/romstage.c27
17 files changed, 754 insertions, 0 deletions
diff --git a/src/mainboard/system76/gaze15/Kconfig b/src/mainboard/system76/gaze15/Kconfig
new file mode 100644
index 0000000000..12f94c2f2b
--- /dev/null
+++ b/src/mainboard/system76/gaze15/Kconfig
@@ -0,0 +1,75 @@
+if BOARD_SYSTEM76_GAZE15
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_16384
+ select DRIVERS_I2C_HID
+ select EC_SYSTEM76_EC
+ select EC_SYSTEM76_EC_BAT_THRESHOLDS
+ select EC_SYSTEM76_EC_COLOR_KEYBOARD
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_LPSS_UART_FOR_CONSOLE
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM2
+ select NO_UART_ON_SUPERIO
+ select SOC_INTEL_CANNONLAKE_PCH_H
+ select SOC_INTEL_COMETLAKE_1
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SPD_READ_BY_WORD
+ select SYSTEM_TYPE_LAPTOP
+
+config MAINBOARD_DIR
+ string
+ default "system76/gaze15"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "gaze15"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+ string
+ default "Gazelle"
+
+config MAINBOARD_VERSION
+ string
+ default "gaze15"
+
+config CBFS_SIZE
+ hex
+ default 0xA00000
+
+config CONSOLE_POST
+ bool
+ default y
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config UART_FOR_CONSOLE
+ int
+ default 2
+
+config MAX_CPUS
+ int
+ default 16
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config VGA_BIOS_ID
+ string
+ default "8086,9bc4"
+
+config POST_DEVICE
+ bool
+ default n
+
+endif
diff --git a/src/mainboard/system76/gaze15/Kconfig.name b/src/mainboard/system76/gaze15/Kconfig.name
new file mode 100644
index 0000000000..dd152081d9
--- /dev/null
+++ b/src/mainboard/system76/gaze15/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_GAZE15
+ bool "gaze15"
diff --git a/src/mainboard/system76/gaze15/Makefile.inc b/src/mainboard/system76/gaze15/Makefile.inc
new file mode 100644
index 0000000000..83ef3a5ca8
--- /dev/null
+++ b/src/mainboard/system76/gaze15/Makefile.inc
@@ -0,0 +1,8 @@
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += gpio_early.c
+
+ramstage-y += ramstage.c
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
diff --git a/src/mainboard/system76/gaze15/acpi/gpe.asl b/src/mainboard/system76/gaze15/acpi/gpe.asl
new file mode 100644
index 0000000000..7ef9a989c0
--- /dev/null
+++ b/src/mainboard/system76/gaze15/acpi/gpe.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_K6 SCI
+Method (_L06, 0, Serialized) {
+ Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+ If (\_SB.PCI0.LPCB.EC0.ECOK) {
+ If (\_SB.PCI0.LPCB.EC0.WFNO == 1) {
+ Notify(\_SB.LID0, 0x80)
+ }
+ }
+}
diff --git a/src/mainboard/system76/gaze15/acpi/mainboard.asl b/src/mainboard/system76/gaze15/acpi/mainboard.asl
new file mode 100644
index 0000000000..4e67439c56
--- /dev/null
+++ b/src/mainboard/system76/gaze15/acpi/mainboard.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x03 /* GPP_K3 */
+#define EC_GPE_SWI 0x06 /* GPP_K6 */
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+ #include "sleep.asl"
+}
+
+Scope (\_GPE) {
+ #include "gpe.asl"
+}
diff --git a/src/mainboard/system76/gaze15/acpi/sleep.asl b/src/mainboard/system76/gaze15/acpi/sleep.asl
new file mode 100644
index 0000000000..48c50e075e
--- /dev/null
+++ b/src/mainboard/system76/gaze15/acpi/sleep.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+ \_SB.PCI0.LPCB.EC0.PTS (Arg0)
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+ \_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}
diff --git a/src/mainboard/system76/gaze15/board_info.txt b/src/mainboard/system76/gaze15/board_info.txt
new file mode 100644
index 0000000000..07130b5699
--- /dev/null
+++ b/src/mainboard/system76/gaze15/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: gaze15
+Category: laptop
+Release year: 2020
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/system76/gaze15/bootblock.c b/src/mainboard/system76/gaze15/bootblock.c
new file mode 100644
index 0000000000..ae416b4e77
--- /dev/null
+++ b/src/mainboard/system76/gaze15/bootblock.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ mainboard_configure_early_gpios();
+}
diff --git a/src/mainboard/system76/gaze15/data.vbt b/src/mainboard/system76/gaze15/data.vbt
new file mode 100644
index 0000000000..a97f225f04
--- /dev/null
+++ b/src/mainboard/system76/gaze15/data.vbt
Binary files differ
diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
new file mode 100644
index 0000000000..e4ca948ff0
--- /dev/null
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -0,0 +1,216 @@
+chip soc/intel/cannonlake
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ // Touchpad I2C bus
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 80,
+ .fall_time_ns = 110,
+ },
+ }"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+ # Power limit
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 45,
+ .tdp_pl2_override = 90,
+ }"
+
+ # Enable Enhanced Intel SpeedStep
+ register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+ register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+ # Serial I/O
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C
+ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console
+ }"
+
+
+ # Misc
+ register "AcousticNoiseMitigation" = "1"
+
+ # Power
+ register "PchPmSlpS3MinAssert" = "3" # 50ms
+ register "PchPmSlpS4MinAssert" = "1" # 1s
+ register "PchPmSlpSusMinAssert" = "4" # 4s
+ register "PchPmSlpAMinAssert" = "4" # 2s
+
+ # Thermal
+ register "tcc_offset" = "8"
+
+ # Serial IRQ Continuous
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "PMC_GPP_K"
+ register "gpe0_dw1" = "PMC_GPP_G"
+ register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ subsystemid 0x1558 0x8520 inherit
+ device pci 00.0 on end # Host Bridge
+ device pci 01.0 on # GPU Port
+ # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
+ register "PcieClkSrcUsage[8]" = "0x40"
+ register "PcieClkSrcClkReq[8]" = "8"
+ end
+ device pci 02.0 on # Integrated Graphics Device
+ register "gfx" = "GMA_DEFAULT_PANEL(0)"
+ end
+ device pci 04.0 on # SA Thermal device
+ register "Device4Enable" = "1"
+ end
+ device pci 12.0 on end # Thermal Subsystem
+ device pci 12.5 off end # UFS SCS
+ device pci 12.6 off end # GSPI #2
+ device pci 13.0 off end # Integrated Sensor Hub
+ device pci 14.0 on # USB xHCI
+ # USB2
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2 Left
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ # USB3
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
+ end
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Shared SRAM
+ device pci 14.3 on # CNVi wifi
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_PME_B0"
+ device generic 0 on end
+ end
+ end
+ device pci 14.5 off end # SDCard
+ device pci 15.0 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""PNP0C50""
+ register "generic.desc" = ""ELAN Touchpad""
+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
+ register "generic.probed" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 15 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""PNP0C50""
+ register "generic.desc" = ""Synaptics Touchpad""
+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
+ register "generic.probed" = "1"
+ register "hid_desc_reg_offset" = "0x20"
+ device i2c 2c on end
+ end
+ end # I2C #0
+ device pci 15.1 on end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 on # SATA
+ register "SataPortsEnable[1]" = "1" # SSD (SATA1A)
+ register "SataPortsEnable[4]" = "1" # HDD (SATA4)
+ end
+ device pci 19.0 off end # I2C #4
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 on end # UART #2
+ device pci 1a.0 off end # eMMC
+ device pci 1b.0 off end # PCI Express Port 17
+ device pci 1b.1 off end # PCI Express Port 18
+ device pci 1b.2 off end # PCI Express Port 19
+ device pci 1b.3 off end # PCI Express Port 20
+ device pci 1b.4 on # PCI Express Port 21
+ # PCI Express root port #21 x4, Clock 11 (SSD2)
+ register "PcieRpEnable[20]" = "1"
+ register "PcieRpLtrEnable[20]" = "1"
+ register "PcieClkSrcUsage[11]" = "20"
+ register "PcieClkSrcClkReq[11]" = "11"
+ register "PcieRpSlotImplemented[20]" = "1"
+ end
+ device pci 1b.5 off end # PCI Express Port 22
+ device pci 1b.6 off end # PCI Express Port 23
+ device pci 1b.7 off end # PCI Express Port 24
+ device pci 1c.0 off end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on # PCI Express Port 9
+ # PCI Express root port #9 x4, Clock 10 (SSD)
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieClkSrcUsage[10]" = "8"
+ register "PcieClkSrcClkReq[10]" = "10"
+ register "PcieRpSlotImplemented[8]" = "1"
+ end
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.4 off end # PCI Express Port 13
+ device pci 1d.5 on # PCI Express Port 14
+ # PCI Express root port #14 x1, Clock 6 (WLAN)
+ register "PcieRpEnable[13]" = "1"
+ register "PcieRpLtrEnable[13]" = "1"
+ register "PcieClkSrcUsage[6]" = "13"
+ register "PcieClkSrcClkReq[6]" = "6"
+ register "PcieRpSlotImplemented[13]" = "1"
+ end
+ device pci 1d.6 on # PCI Express Port 15
+ # PCI Express root port #15 x1, Clock 5 (LAN)
+ register "PcieRpEnable[14]" = "1"
+ register "PcieRpLtrEnable[14]" = "1"
+ register "PcieClkSrcUsage[5]" = "14"
+ register "PcieClkSrcClkReq[5]" = "5"
+ register "PcieRpSlotImplemented[14]" = "1"
+ end
+ device pci 1d.7 off end # PCI Express Port 16
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 on # LPC Interface
+ register "gen1_dec" = "0x000c0081"
+ register "gen2_dec" = "0x00040069"
+ register "gen3_dec" = "0x00fc0e01"
+ register "gen4_dec" = "0x00fc0f01"
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 off end # Power Management Controller
+ device pci 1f.3 on # Intel HDA
+ register "PchHdaAudioLinkHda" = "1"
+ register "PchHdaAudioLinkDmic0" = "1"
+ register "PchHdaAudioLinkDmic1" = "1"
+ end
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/system76/gaze15/dsdt.asl b/src/mainboard/system76/gaze15/dsdt.asl
new file mode 100644
index 0000000000..8a3b4d7904
--- /dev/null
+++ b/src/mainboard/system76/gaze15/dsdt.asl
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include <soc/intel/common/block/acpi/acpi/platform.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Device (\_SB.PCI0) {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/cannonlake/acpi/southbridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Scope (\_SB.PCI0.LPCB) {
+ #include <drivers/pc80/pc/ps2_controller.asl>
+ }
+
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/system76/gaze15/gpio.c b/src/mainboard/system76/gaze15/gpio.c
new file mode 100644
index 0000000000..fcd716c50f
--- /dev/null
+++ b/src/mainboard/system76/gaze15/gpio.c
@@ -0,0 +1,277 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+ /* ------- GPIO Group GPD ------- */
+ PAD_CFG_GPI(GPD0, NONE, PWROK), // PM_BATLOW#
+ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+ PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
+ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#
+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#
+ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A# (test point)
+ PAD_CFG_GPI(GPD7, NONE, PWROK), /* GPD_7 (crystal input,
+ low = signal ended,
+ high = differential)
+ */
+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK_R
+ PAD_NC(GPD9, UP_20K), // PCH_SLP_WLAN# (test point)
+ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // NC
+ PAD_NC(GPD11, UP_20K), // LAN_DISABLE_N (test point)
+
+ /* ------- GPIO Group GPP_A ------- */
+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
+ _PAD_CFG_STRUCT(GPP_A7, 0x80100100, 0x0000), // INTP_OUT
+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // CLK_PCI_KBC_R
+ PAD_NC(GPP_A10, UP_20K),
+ PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // LAN_WUP#
+ PAD_NC(GPP_A12, UP_20K), // ISH_GP_6_R (test point)
+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
+ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // S4_STATE#
+ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK#_R
+ PAD_NC(GPP_A16, UP_20K),
+ PAD_NC(GPP_A17, UP_20K),
+ PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
+ PAD_NC(GPP_A19, UP_20K),
+ PAD_NC(GPP_A20, UP_20K),
+ PAD_NC(GPP_A21, UP_20K), // 3G_CONFIG2 (test point)
+ PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // SATA_PWR_EN
+ PAD_NC(GPP_A23, UP_20K), // DGPU_PWM_SELECT# (test point)
+
+ /* ------- GPIO Group GPP_B ------- */
+ PAD_CFG_GPI(GPP_B0, NONE, DEEP),// TPM_PIRQ#
+ PAD_NC(GPP_B1, UP_20K), // GPP_B1 (test point)
+ PAD_NC(GPP_B2, UP_20K), // VRALERTB# (test point)
+ PAD_CFG_GPI(GPP_B3, NONE, DEEP), // BT_EN_PCH
+ PAD_CFG_GPI(GPP_B4, UP_20K, DEEP), // EXTTS_SNI_DRV1
+ PAD_NC(GPP_B5, UP_20K),
+ PAD_NC(GPP_B6, UP_20K),
+ PAD_NC(GPP_B7, UP_20K),
+ PAD_NC(GPP_B8, UP_20K),
+ PAD_NC(GPP_B9, UP_20K),
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ#
+ PAD_NC(GPP_B11, UP_20K),
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // SPKR_SMC_EXTSMI (PCH_SPKR)
+ PAD_NC(GPP_B15, UP_20K),
+ PAD_NC(GPP_B16, UP_20K),
+ PAD_NC(GPP_B17, UP_20K),
+ PAD_CFG_GPI(GPP_B18, NONE, DEEP), // LPSS_GSPI0_MOSI (no reboot)
+ PAD_NC(GPP_B19, UP_20K),
+ PAD_NC(GPP_B20, UP_20K),
+ PAD_NC(GPP_B21, UP_20K),
+ PAD_CFG_GPI(GPP_B22, NONE, DEEP), // LPSS_GSPI1_MOSI (boot strap)
+ PAD_CFG_GPI(GPP_B23, NONE, DEEP), // PCH_HOT_GNSS_DISABLE
+
+ /* ------- GPIO Group GPP_C ------- */
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+ PAD_CFG_GPI(GPP_C2, NONE, DEEP), // SKIN_THRM_SNSR_ALERT_N
+ PAD_CFG_GPI(GPP_C3, NONE, DEEP), // SML0_CLK
+ PAD_CFG_GPI(GPP_C4, NONE, DEEP), // SMK0_DATA
+ PAD_NC(GPP_C5, UP_20K), // GPP_C5 (test point)
+ PAD_CFG_GPI(GPP_C6, NONE, DEEP), // SMC_CPU_THERM
+ PAD_CFG_GPI(GPP_C7, NONE, DEEP), // SMD_CPU_THERM
+ PAD_NC(GPP_C8, UP_20K),
+ PAD_NC(GPP_C9, UP_20K),
+ PAD_NC(GPP_C10, UP_20K),
+ PAD_NC(GPP_C11, UP_20K),
+ PAD_NC(GPP_C12, UP_20K),
+ PAD_NC(GPP_C13, UP_20K),
+ PAD_NC(GPP_C14, UP_20K),
+ PAD_NC(GPP_C15, UP_20K),
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // SMD_7411_I2C
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // SMC_7411_I2C
+ //PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+ //PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+ PAD_NC(GPP_C22, UP_20K),
+ PAD_NC(GPP_C23, UP_20K),
+
+ /* ------- GPIO Group GPP_D ------- */
+ PAD_NC(GPP_D0, UP_20K),
+ PAD_NC(GPP_D1, UP_20K),
+ PAD_NC(GPP_D2, UP_20K),
+ PAD_NC(GPP_D3, UP_20K),
+ PAD_CFG_GPI(GPP_D4, NONE, DEEP), // I2C2_SDA
+ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST#
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
+ PAD_NC(GPP_D7, UP_20K),
+ PAD_NC(GPP_D8, UP_20K),
+ PAD_NC(GPP_D9, UP_20K),
+ PAD_NC(GPP_D10, UP_20K),
+ PAD_NC(GPP_D11, UP_20K),
+ PAD_NC(GPP_D12, UP_20K),
+ PAD_NC(GPP_D13, UP_20K),
+ PAD_NC(GPP_D14, UP_20K),
+ PAD_NC(GPP_D15, UP_20K),
+ PAD_NC(GPP_D16, UP_20K),
+ PAD_NC(GPP_D17, NONE), // 100k pull down
+ PAD_NC(GPP_D18, UP_20K),
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // MIC_CLK_PCH_R
+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // MIC_DATA_PCH_R
+ PAD_NC(GPP_D21, UP_20K),
+ PAD_NC(GPP_D22, UP_20K),
+ PAD_CFG_GPI(GPP_D23, NONE, DEEP), // I2C2_SCL
+
+ /* ------- GPIO Group GPP_E ------- */
+ PAD_NC(GPP_E0, UP_20K), // SATAGP0 (test point)
+ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SATAGP2
+ PAD_CFG_GPI(GPP_E3, NONE, DEEP), // EXTTS_SNI_DRV0
+ PAD_CFG_GPI(GPP_E4, NONE, DEEP), // DEVSLP0
+ PAD_CFG_GPI(GPP_E5, NONE, DEEP), // DEVSLP1
+ PAD_NC(GPP_E6, UP_20K), // PCH_MUTE# (test point)
+ PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN#
+ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
+ PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0#
+ PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1#
+ PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2#
+ PAD_CFG_GPI(GPP_E12, NONE, DEEP), // VISACH2_D3
+
+ /* ------- GPIO Group GPP_F ------- */
+ PAD_CFG_GPI(GPP_F0, NONE, DEEP), // SATAGP3
+ PAD_NC(GPP_F1, UP_20K),
+ PAD_NC(GPP_F2, UP_20K), // ODD_DA#_R (test point)
+ PAD_NC(GPP_F3, UP_20K), // (test point)
+ PAD_NC(GPP_F4, UP_20K),
+ PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET
+ PAD_CFG_GPI(GPP_F6, NONE, DEEP), // DEVSLP4
+ PAD_CFG_GPI(GPP_F7, NONE, DEEP), // LIGHT_KB_DET#
+ PAD_CFG_GPI(GPP_F8, NONE, DEEP), // GPP_F8
+ PAD_CFG_GPI(GPP_F9, NONE, DEEP), // GPP_F9
+ PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC
+ PAD_CFG_GPI(GPP_F11, NONE, DEEP), // PCH_RSVD
+ PAD_CFG_GPI(GPP_F12, NONE, DEEP), // MFG_MODE
+ PAD_CFG_GPI(GPP_F13, NONE, DEEP), // GP39_GFX_CRB_DETECT
+ PAD_CFG_GPI(GPP_F14, NONE, DEEP), // 10k pull up to H_SKTOCC_N
+ PAD_CFG_GPI(GPP_F15, NONE, DEEP), // USB_OC4#
+ PAD_CFG_GPI(GPP_F16, NONE, DEEP), // USB_OC5#
+ PAD_CFG_GPI(GPP_F17, NONE, DEEP), // USB_OC6#
+ PAD_CFG_GPI(GPP_F18, NONE, DEEP), // USB_OC7#
+ //PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
+ //PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
+ //PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
+
+ /* ------- GPIO Group GPP_G ------- */
+ PAD_CFG_GPI(GPP_G0, UP_20K, DEEP), // BOARD_ID1
+ PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2
+ PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET
+ PAD_CFG_GPI(GPP_G3, NONE, DEEP), // GPIO4_1V8_MAIN_EN_R
+ PAD_CFG_GPI(GPP_G4, NONE, DEEP), // SMI#_R
+ PAD_NC(GPP_G5, UP_20K),
+ PAD_NC(GPP_G6, UP_20K),
+ PAD_NC(GPP_G7, UP_20K),
+
+ /* ------- GPIO Group GPP_H ------- */
+ PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
+ PAD_NC(GPP_H1, UP_20K),
+ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
+ PAD_NC(GPP_H3, UP_20K),
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ#
+ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ#
+ PAD_NC(GPP_H6, UP_20K),
+ PAD_NC(GPP_H7, UP_20K),
+ PAD_NC(GPP_H8, UP_20K),
+ PAD_NC(GPP_H9, UP_20K),
+ PAD_NC(GPP_H10, UP_20K), // SML2CLK (test point)
+ PAD_NC(GPP_H11, UP_20K), // SML2DATA (test point)
+ PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H_12 (eSPI flash sharing)
+ PAD_CFG_GPI(GPP_H13, NONE, DEEP), // SML3CLK
+ PAD_NC(GPP_H14, UP_20K), // SML3DATA (test point)
+ PAD_CFG_GPI(GPP_H15, NONE, DEEP), // SML3ALERT#
+ PAD_NC(GPP_H16, UP_20K), // SML4CLK (test point)
+ PAD_NC(GPP_H17, UP_20K), // SML4DATA (test point)
+ PAD_NC(GPP_H18, UP_20K), // SML4ALERT# (test point)
+ PAD_NC(GPP_H19, UP_20K),
+ PAD_NC(GPP_H20, UP_20K),
+ PAD_NC(GPP_H21, UP_20K),
+ PAD_NC(GPP_H22, UP_20K),
+ PAD_CFG_GPI(GPP_H23, NONE, DEEP), // DGPU_SELECT#
+
+ /* ------- GPIO Group GPP_I ------- */
+ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* I_MDP_HPD on 1660 Ti,
+ NC on 1650/1650 Ti
+ */
+ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD
+ PAD_CFG_GPI(GPP_I2, NONE, DEEP), // 1k pull to MDP_E_HPD
+ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // 1k pull to MDP_E_HPD
+ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD
+ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), /* I_MDP_CLK (on 1660 Ti),
+ NC (on 1650/1650 Ti)
+ */
+ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), /* I_MDP_DATA (on 1660 Ti),
+ NC (on 1650/1650 Ti)
+ */
+ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* HDMI_CTRLCLK (on 1650/1650 Ti),
+ test point (on 1660 Ti)
+ */
+ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* HDMI_CTRLDATA (on 1650/1650 Ti),
+ test point (on 1660 Ti)
+ */
+ PAD_NC(GPP_I9, UP_20K),
+ PAD_NC(GPP_I10, UP_20K),
+ PAD_CFG_GPI(GPP_I11, NONE, DEEP), // 10k pull up to H_SKTOCC_N
+ PAD_NC(GPP_I12, UP_20K),
+ PAD_NC(GPP_I13, UP_20K),
+ PAD_NC(GPP_I14, UP_20K),
+
+ /* ------- GPIO Group GPP_J ------- */
+ PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+ PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), // GPP_J1
+ PAD_NC(GPP_J2, NONE), // 100k pull down
+ PAD_NC(GPP_J3, NONE), // 100k pull down
+ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
+ PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
+ PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+ PAD_NC(GPP_J10, UP_20K),
+ PAD_NC(GPP_J11, NONE), // 75k pull down
+
+ /* ------- GPIO Group GPP_K ------- */
+ PAD_NC(GPP_K0, UP_20K), // PCH_GPPK0_PCH_PEXVDD_EN (test point)
+ PAD_NC(GPP_K1, UP_20K), // PCH_GPPK1_PCH_FBVDDQ_EN (test point)
+ PAD_NC(GPP_K2, UP_20K), // PCH_GPPK2_PCH_1V8RUN_EN (test point)
+ _PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x0000), // SCI#_R
+ PAD_NC(GPP_K4, UP_20K),
+ PAD_NC(GPP_K5, UP_20K),
+ _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_R
+ PAD_NC(GPP_K7, UP_20K),
+ PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // SATA_M2_PWR_EN1
+ PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP), // SATA_M2_PWR_EN2
+ PAD_NC(GPP_K10, UP_20K), // PCH_GPPK10_PCH_NVVDD_EN (test point)
+ PAD_NC(GPP_K11, UP_20K), // PCH_GPPK11_PCH_NVVDD_EN (test point)
+ PAD_NC(GPP_K12, UP_20K), // (test point)
+ PAD_NC(GPP_K13, UP_20K),
+ PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), // GPP_K14_TEST_R
+ PAD_NC(GPP_K15, UP_20K),
+ PAD_NC(GPP_K16, UP_20K), // (test point)
+ PAD_NC(GPP_K17, UP_20K),
+ PAD_NC(GPP_K18, UP_20K),
+ PAD_CFG_GPI(GPP_K19, NONE, DEEP), // SMI#_RR
+ PAD_CFG_TERM_GPO(GPP_K20, 1, NONE, DEEP), // GPU_EVENT#
+ PAD_CFG_GPI(GPP_K21, NONE, PLTRST), // GC6_FB_EN_PCH
+ PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R
+ PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PRSNT#
+};
+
+void mainboard_configure_gpios(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/gaze15/gpio_early.c b/src/mainboard/system76/gaze15/gpio_early.c
new file mode 100644
index 0000000000..f1a4c92e3a
--- /dev/null
+++ b/src/mainboard/system76/gaze15/gpio_early.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+ PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST#_PCH
+ PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
+};
+
+void mainboard_configure_early_gpios(void)
+{
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/gaze15/hda_verb.c b/src/mainboard/system76/gaze15/hda_verb.c
new file mode 100644
index 0000000000..1540485862
--- /dev/null
+++ b/src/mainboard/system76/gaze15/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* Realtek, ALC293 */
+ 0x10ec0293, /* Vendor ID */
+ 0x15588520, /* Subsystem ID */
+ 12, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x15588520),
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x02a11040),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/gaze15/include/mainboard/gpio.h b/src/mainboard/system76/gaze15/include/mainboard/gpio.h
new file mode 100644
index 0000000000..c6393beebb
--- /dev/null
+++ b/src/mainboard/system76/gaze15/include/mainboard/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_early_gpios(void);
+void mainboard_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/system76/gaze15/ramstage.c b/src/mainboard/system76/gaze15/ramstage.c
new file mode 100644
index 0000000000..ae2d7414d8
--- /dev/null
+++ b/src/mainboard/system76/gaze15/ramstage.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <device/device.h>
+
+static void init_mainboard(void *chip_info)
+{
+ mainboard_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+ .init = init_mainboard,
+};
diff --git a/src/mainboard/system76/gaze15/romstage.c b/src/mainboard/system76/gaze15/romstage.c
new file mode 100644
index 0000000000..6309e4a42a
--- /dev/null
+++ b/src/mainboard/system76/gaze15/romstage.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+ .spd[0] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xa0},
+ },
+ .spd[2] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xa4},
+ },
+ .rcomp_resistor = { 121, 75, 100 },
+ .rcomp_targets = { 50, 25, 20, 20, 26 },
+ .dq_pins_interleaved = 1,
+ .vref_ca_config = 2,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+ // Allow memory speeds higher than 2933 MT/s
+ memupd->FspmConfig.SaOcSupport = 1;
+
+ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 10:06:31 +0000