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-rw-r--r--src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb4
-rw-r--r--src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb4
-rw-r--r--src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb4
-rw-r--r--src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb4
-rw-r--r--src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb4
-rw-r--r--src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb3
6 files changed, 0 insertions, 23 deletions
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
index d03bd2e432..ad90eabfee 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
@@ -53,21 +53,18 @@ chip soc/intel/tigerlake
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 5 (GLAN)
- register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieClkSrcUsage[5]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
end
device ref pcie_rp7 on
# PCIe root port #7 x1, Clock 7 (CARD)
- register "PcieRpEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieClkSrcUsage[7]" = "6"
register "PcieClkSrcClkReq[7]" = "7"
end
device ref pcie_rp8 on
# PCIe root port #8 x1, Clock 8 (WLAN)
- register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieClkSrcUsage[8]" = "7"
register "PcieClkSrcClkReq[8]" = "8"
@@ -75,7 +72,6 @@ chip soc/intel/tigerlake
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 9 (SSD1)
- register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[9]" = "8"
register "PcieClkSrcClkReq[9]" = "9"
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
index b463fe7b7b..bfbc5c5090 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
@@ -53,21 +53,18 @@ chip soc/intel/tigerlake
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 8 (GLAN)
- register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
#register "PcieClkSrcUsage[8]" = "4"
register "PcieClkSrcClkReq[8]" = "8"
end
device ref pcie_rp7 on
# PCIe root port #7 x1, Clock 3 (CARD)
- register "PcieRpEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieClkSrcUsage[3]" = "6"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp8 on
# PCIe root port #8 x1, Clock 2 (WLAN)
- register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieClkSrcUsage[2]" = "7"
register "PcieClkSrcClkReq[2]" = "2"
@@ -75,7 +72,6 @@ chip soc/intel/tigerlake
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 10 (SSD2)
- register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[10]" = "8"
register "PcieClkSrcClkReq[10]" = "10"
diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
index 6f25d7bb7c..a09cf30cad 100644
--- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
@@ -62,21 +62,18 @@ chip soc/intel/tigerlake
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 8 (GLAN)
- register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieClkSrcUsage[8]" = "4"
register "PcieClkSrcClkReq[8]" = "8"
end
device ref pcie_rp6 on
# PCIe root port #6 x1, Clock 10 (CARD)
- register "PcieRpEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieClkSrcUsage[10]" = "5"
register "PcieClkSrcClkReq[10]" = "10"
end
device ref pcie_rp8 on
# PCIe root port #8 x1, Clock 2 (WLAN)
- register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieClkSrcUsage[2]" = "7"
register "PcieClkSrcClkReq[2]" = "2"
@@ -84,7 +81,6 @@ chip soc/intel/tigerlake
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 6 (SSD2)
- register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[6]" = "8"
register "PcieClkSrcClkReq[6]" = "6"
diff --git a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
index 9a669ef7fd..a35dc52ab9 100644
--- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
@@ -141,14 +141,12 @@ chip soc/intel/tigerlake
end
device ref pcie_rp6 on
# PCIe root port #6 x1, Clock 2 (CARD)
- register "PcieRpEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieClkSrcUsage[2]" = "5"
register "PcieClkSrcClkReq[2]" = "2"
end
device ref pcie_rp7 on
# PCIe root port #7 x1, Clock 3 (GLAN)
- register "PcieRpEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieClkSrcUsage[3]" = "6"
register "PcieClkSrcClkReq[3]" = "3"
@@ -161,7 +159,6 @@ chip soc/intel/tigerlake
end
device ref pcie_rp8 on
# PCIe root port #8 x1, Clock 1 (WLAN)
- register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieClkSrcUsage[1]" = "7"
register "PcieClkSrcClkReq[1]" = "1"
@@ -169,7 +166,6 @@ chip soc/intel/tigerlake
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 4 (SSD0)
- register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[4]" = "8"
register "PcieClkSrcClkReq[4]" = "4"
diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
index 7c3475e466..075a2e44ab 100644
--- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
@@ -141,7 +141,6 @@ chip soc/intel/tigerlake
end
device ref pcie_rp5 on
# PCIe root port #5 x4, Clock 2 (NVIDIA GPU)
- register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieClkSrcUsage[2]" = "4"
register "PcieClkSrcClkReq[2]" = "2"
@@ -158,14 +157,12 @@ chip soc/intel/tigerlake
end
device ref pcie_rp9 on
# PCIe root port #9 x1, Clock 3 (CARD)
- register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 on
# PCIe root port #10 x1, Clock 4 (GLAN)
- register "PcieRpEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "1"
register "PcieClkSrcUsage[4]" = "9"
register "PcieClkSrcClkReq[4]" = "4"
@@ -178,7 +175,6 @@ chip soc/intel/tigerlake
end
device ref pcie_rp11 on
# PCIe root port #11 x1, Clock 1 (WLAN)
- register "PcieRpEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
register "PcieClkSrcUsage[1]" = "10"
register "PcieClkSrcClkReq[1]" = "1"
diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
index 671cdc4a54..ce4507900e 100644
--- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
@@ -118,7 +118,6 @@ chip soc/intel/tigerlake
end
device ref pcie_rp3 on
# PCIe root port #3 x1, Clock 1 (WLAN)
- register "PcieRpEnable[2]" = "1"
register "PcieRpLtrEnable[2]" = "1"
register "PcieClkSrcUsage[1]" = "2"
register "PcieClkSrcClkReq[1]" = "1"
@@ -126,7 +125,6 @@ chip soc/intel/tigerlake
end
device ref pcie_rp6 on
# PCIe root port #6 x1, Clock 2 (CARD)
- register "PcieRpEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieClkSrcUsage[2]" = "5"
register "PcieClkSrcClkReq[2]" = "2"
@@ -134,7 +132,6 @@ chip soc/intel/tigerlake
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 0 (SSD2)
# Despite the name, SSD1_CLKREQ# is used for SSD2
- register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[0]" = "8"
register "PcieClkSrcClkReq[0]" = "0"
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-25 06:33:26 +0000