diff options
Diffstat (limited to 'src/mainboard/system76/tgl-u')
21 files changed, 862 insertions, 0 deletions
diff --git a/src/mainboard/system76/tgl-u/Kconfig b/src/mainboard/system76/tgl-u/Kconfig new file mode 100644 index 0000000000..fdf7a5c6d3 --- /dev/null +++ b/src/mainboard/system76/tgl-u/Kconfig @@ -0,0 +1,62 @@ +if BOARD_SYSTEM76_LEMP10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select EC_SYSTEM76_EC + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select HAVE_SPD_IN_CBFS if BOARD_SYSTEM76_LEMP10 + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select PCIEXP_HOTPLUG + select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G + select SOC_INTEL_TIGERLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM_MEASURED_BOOT + select TPM_RDRESP_NEED_DELAY + +config MAINBOARD_DIR + default "system76/tgl-u" + +config VARIANT_DIR + default "lemp10" if BOARD_SYSTEM76_LEMP10 + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_PART_NUMBER + default "lemp10" if BOARD_SYSTEM76_LEMP10 + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Lemur Pro" if BOARD_SYSTEM76_LEMP10 + +config MAINBOARD_VERSION + default "lemp10" if BOARD_SYSTEM76_LEMP10 + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config POST_DEVICE + default n + +config UART_FOR_CONSOLE + default 2 + +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + +endif diff --git a/src/mainboard/system76/tgl-u/Kconfig.name b/src/mainboard/system76/tgl-u/Kconfig.name new file mode 100644 index 0000000000..43aae91b99 --- /dev/null +++ b/src/mainboard/system76/tgl-u/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SYSTEM76_LEMP10 + bool "lemp10" diff --git a/src/mainboard/system76/tgl-u/Makefile.inc b/src/mainboard/system76/tgl-u/Makefile.inc new file mode 100644 index 0000000000..8857a3bf66 --- /dev/null +++ b/src/mainboard/system76/tgl-u/Makefile.inc @@ -0,0 +1,12 @@ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c + +SPD_SOURCES = samsung-M471A1G44AB0-CWE diff --git a/src/mainboard/system76/tgl-u/acpi/mainboard.asl b/src/mainboard/system76/tgl-u/acpi/mainboard.asl new file mode 100644 index 0000000000..4675bc94b8 --- /dev/null +++ b/src/mainboard/system76/tgl-u/acpi/mainboard.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#include <ec/system76/ec/acpi/ec.asl> + +Scope (\_SB) { + #include "sleep.asl" +} diff --git a/src/mainboard/system76/tgl-u/acpi/sleep.asl b/src/mainboard/system76/tgl-u/acpi/sleep.asl new file mode 100644 index 0000000000..83888f3e59 --- /dev/null +++ b/src/mainboard/system76/tgl-u/acpi/sleep.asl @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/gpio.h> + +Method (PGPM, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + PGPM (0) + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + } Else { + /* S0ix Exit */ + PGPM (0) + } +} diff --git a/src/mainboard/system76/tgl-u/board_info.txt b/src/mainboard/system76/tgl-u/board_info.txt new file mode 100644 index 0000000000..badfb66706 --- /dev/null +++ b/src/mainboard/system76/tgl-u/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: System76 +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/tgl-u/bootblock.c b/src/mainboard/system76/tgl-u/bootblock.c new file mode 100644 index 0000000000..ae416b4e77 --- /dev/null +++ b/src/mainboard/system76/tgl-u/bootblock.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <gpio.h> +#include <mainboard/gpio.h> + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default new file mode 100644 index 0000000000..62715bc6ba --- /dev/null +++ b/src/mainboard/system76/tgl-u/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +me_state=Enable diff --git a/src/mainboard/system76/tgl-u/cmos.layout b/src/mainboard/system76/tgl-u/cmos.layout new file mode 100644 index 0000000000..a53c3f4bba --- /dev/null +++ b/src/mainboard/system76/tgl-u/cmos.layout @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter +984 16 h 0 check_sum + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 983 984 diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb new file mode 100644 index 0000000000..9c91c17368 --- /dev/null +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -0,0 +1,134 @@ +chip soc/intel/tigerlake + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# ACPI (soc/intel/tigerlake/acpi.c) + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable s0ix, required for TGL-U + register "s0ix_enable" = "1" + +# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) + # Enable C6 DRAM + register "enable_c6dram" = "1" + + # System Agent dynamic frequency support + register "SaGv" = "SaGv_Enabled" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SLEW_FAST_8" + register "FastPkgCRampDisable" = "1" + + # FIVR configuration + # Read EXT_RAIL_CONFIG to determine bitmaps + # sudo devmem2 0xfe0011b8 + # 0x0 + # Read EXT_V1P05_VR_CONFIG + # sudo devmem2 0xfe0011c0 + # 0x1a42000 + # Read EXT_VNN_VR_CONFIG0 + # sudo devmem2 0xfe0011c4 + # 0x1a42000 + # TODO: v1p05 voltage and vnn icc max? + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = 0, + .vnn_enable_bitmap = 0, + .v1p05_supported_voltage_bitmap = 0, + .vnn_supported_voltage_bitmap = 0, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1050, + }" + + # Read LPM_EN, make sure to invert the bits + register "LpmStateDisableMask" = " + LPM_S0i2_1 | + LPM_S0i2_2 | + LPM_S0i3_1 | + LPM_S0i3_2 | + LPM_S0i3_3 | + LPM_S0i3_4 + " + + # Thermal + register "tcc_offset" = "12" + + # Enable CNVi BT + register "CnviBtCore" = "true" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device ref system_agent on end + device ref igpu on + # DDIA is eDP + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" + + # DDIB is HDMI + register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" + register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref dptf on end + device ref tbt_pcie_rp0 on end + device ref gna on end + device ref shared_ram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref i2c1 on + # TODO: USB-PD? + register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref heci1 on end + device ref uart2 on + # Debug console + register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" + end + device ref pch_espi on + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00fc0E01" + register "gen3_dec" = "0x00fc0F01" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref p2sb on end + device ref hda on + register "PchHdaAudioLinkHdaEnable" = "1" + end + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/system76/tgl-u/dsdt.asl b/src/mainboard/system76/tgl-u/dsdt.asl new file mode 100644 index 0000000000..fb40a5d67f --- /dev/null +++ b/src/mainboard/system76/tgl-u/dsdt.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/tigerlake/acpi/tcss.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/tgl-u/include/mainboard/gpio.h b/src/mainboard/system76/tgl-u/include/mainboard/gpio.h new file mode 100644 index 0000000000..c6393beebb --- /dev/null +++ b/src/mainboard/system76/tgl-u/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/system76/tgl-u/ramstage.c b/src/mainboard/system76/tgl-u/ramstage.c new file mode 100644 index 0000000000..dd7e73c595 --- /dev/null +++ b/src/mainboard/system76/tgl-u/ramstage.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Disable AER to fix suspend failing with some SSDs. + params->CpuPcieRpAdvancedErrorReporting[0] = 0; +} + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/system76/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex b/src/mainboard/system76/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex new file mode 100644 index 0000000000..d07aee2572 --- /dev/null +++ b/src/mainboard/system76/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex @@ -0,0 +1,33 @@ +# Samsung M471A1G44AB0-CWE +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 47 +34 34 41 42 30 2D 43 57 45 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/board_info.txt b/src/mainboard/system76/tgl-u/variants/lemp10/board_info.txt new file mode 100644 index 0000000000..abdde03ff4 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/lemp10/board_info.txt @@ -0,0 +1,2 @@ +Board name: lemp10 +Release year: 2020 diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/data.vbt b/src/mainboard/system76/tgl-u/variants/lemp10/data.vbt Binary files differnew file mode 100644 index 0000000000..7c29ceda62 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/lemp10/data.vbt diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c b/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c new file mode 100644 index 0000000000..cca2056450 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_GPI(GPD2, NONE, PWROK), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A# - test point + PAD_CFG_GPO(GPD7, 1, PWROK), // GPD7_REST + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, PWROK), // GPD9_RTD3 + PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), // SLP_S5# - test point + PAD_CFG_GPI(GPD11, UP_20K, DEEP), + + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO_0 + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO_1 + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO_2 + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO_3 + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_N + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET_N + PAD_NC(GPP_A7, NONE), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), // CNVI_RST# + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), // CNVI_CLKREQ + PAD_NC(GPP_A10, NONE), // GPPC_DMIC_DATA + PAD_NC(GPP_A11, NONE), + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), // SATAGP1 + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN + PAD_NC(GPP_A14, NONE), // GPPC_DMIC_CLK + PAD_NC(GPP_A15, NONE), // USB_OC2# + PAD_NC(GPP_A16, NONE), // USB_OC3# + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_CFG_GPO(GPP_A23, 0, PLTRST), // TC_RETIMER_FORCE_PWR + + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + PAD_CFG_GPI(GPP_B2, UP_20K, DEEP), // VRALERT# + PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), // GPP_B3 - touchpad interrupt + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), // PCH_FLASH_I2C_SDA - test point + PAD_NC(GPP_B6, NONE), // PCH_FLASH_I2C_SCL - test point + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA_I2C_INT + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_GPO(GPP_B14, 0, DEEP), // PCH_SPKR + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), // PCH_GPP_B16 - test point + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), // PCH_GPP_B18 - No reboot strap + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_GPO(GPP_B23, 0, DEEP), // GPP_B23 + + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPO(GPP_C2, 1, DEEP), // PCH_GPP_C2 - ME TLS strap + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA + PAD_NC(GPP_C5, NONE), // PCH_GPP_C5 - boot strap bit 0 + PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1), // TBT_I2C_SCL + PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1), // TBT_I2C_SDA + PAD_NC(GPP_C8, NONE), + _PAD_CFG_STRUCT(GPP_C9, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_CFG_GPO(GPP_C13, 1, PLTRST), // SSD1_PWR_DN# + PAD_NC(GPP_C14, DN_20K), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_C22, 1, PLTRST), // GPP_C12_RTD3 + _PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000), // PCH_GPP_C23 + + PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON + PAD_CFG_GPI(GPP_D1, NONE, DEEP), // DDR_TYPE_D1 + PAD_CFG_GPI(GPP_D2, DN_20K, DEEP), // LEDKB_DET# + PAD_CFG_GPI(GPP_D3, DN_20K, DEEP), // BOARD_ID + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD1_CLKREQ# + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // CARD_CLKREQ# + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // SSD2_CLKREQ# + PAD_CFG_GPO(GPP_D9, 1, PLTRST), // GPP_D13_RTD3 - schematics name incorrect + PAD_NC(GPP_D10, NONE), // GPP_D10 - I2C / TBT_LSX2 pin voltage (L=1.8V, H=3.3V) + PAD_CFG_GPI(GPP_D11, DN_20K, DEEP), + PAD_NC(GPP_D12, NONE), // GPP_D12 - I2C / TBT_LSX3 pin voltage (L=1.8V, H=3.3V) + PAD_NC(GPP_D13, NONE), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD2_PWR_DN# + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_GPI(GPP_D17, NONE, DEEP), // DDR_TYPE_D17 + PAD_CFG_GPI(GPP_D18, NONE, DEEP), // DDR_TYPE_D18 + PAD_NC(GPP_D19, NONE), + + PAD_NC(GPP_E0, NONE), + PAD_CFG_GPO(GPP_E1, 0, PLTRST), // ROM_I2C_EN + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPI(GPP_E3, DN_20K, DEEP), // SB_KBCRST# + PAD_NC(GPP_E4, NONE), // DEVSLP0 + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // DEVSLP1 + PAD_NC(GPP_E6, NONE), // PCH_GPP_E6 - reserved strap + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), // USB_OC0# + PAD_NC(GPP_E10, NONE), // PCH_GPP_E10 - THC0_SPI1 chip select + PAD_NC(GPP_E11, NONE), // PCH_GPP_E11 - THC0_SPI1 clock + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD + PAD_CFG_GPI(GPP_E15, DN_20K, DEEP), // SCI# + _PAD_CFG_STRUCT(GPP_E16, 0x82840100, 0x0000), // SMI# + PAD_NC(GPP_E17, NONE), + PAD_NC(GPP_E18, NONE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 + PAD_NC(GPP_E19, NONE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 + _PAD_CFG_STRUCT(GPP_E20, 0x40880100, 0x0000), // SWI# + PAD_NC(GPP_E21, NONE), // GPP_E21 - DDP2 I2C / TBT_LSX1 pin voltage (L=1.8V, H=3.3V) + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), // CNVI_GNSS_PA_BLANKING + PAD_NC(GPP_F7, NONE), // GPP_F7 - reserved strap + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), // GPP_F10 - reserved strap + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPI(GPP_F17, NONE, PLTRST), // TPM_DET# + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), // EXT_PWR_GATE# + PAD_CFG_GPI(GPP_F21, DN_20K, DEEP), // EXT_PWR_GATE2# + PAD_NC(GPP_F22, NONE), // VNN_CTRL + PAD_NC(GPP_F23, NONE), // V1P05_CTRL + + PAD_NC(GPP_H0, DN_20K), // GPP_H0 - boot strap bit 1 + PAD_NC(GPP_H1, DN_20K), // GPP_H1 - boot strap bit 2 + PAD_NC(GPP_H2, DN_20K), // GPP_H2 - boot strap bit 3 + PAD_CFG_GPI(GPP_H3, DN_20K, DEEP), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_CFG_GPI(GPP_H6, NONE, DEEP), // test point + PAD_NC(GPP_H7, NONE), // test point + PAD_CFG_GPI(GPP_H8, DN_20K, DEEP), // CNVI_MFUART2_RXD + PAD_CFG_GPI(GPP_H9, DN_20K, DEEP), // CNVI_MFUART2_TXD + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), // G_INT1 + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), // HDMI_CTRLCLK + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_NC(GPP_H19, NONE), // CNVI_WAKE# + PAD_NC(GPP_H20, NONE), // PM_CLKRUN# + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), + + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_CFG_GPI(GPP_S6, NONE, DEEP), + PAD_CFG_GPI(GPP_S7, NONE, DEEP), + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), + PAD_NC(GPP_U4, NONE), + PAD_NC(GPP_U5, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/gpio_early.c b/src/mainboard/system76/tgl-u/variants/lemp10/gpio_early.c new file mode 100644 index 0000000000..80f37c6553 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/lemp10/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c b/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c new file mode 100644 index 0000000000..1259ba10ff --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x155814a1, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x155814a1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41748245), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb new file mode 100644 index 0000000000..3be5b5ceab --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb @@ -0,0 +1,163 @@ +chip soc/intel/tigerlake + # Power limits + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_R" + register "pmc_gpe0_dw1" = "PMC_GPP_B" + register "pmc_gpe0_dw2" = "PMC_GPP_D" + + device domain 0 on + subsystemid 0x1558 0x14a1 inherit + + device ref peg on + # PCIe PEG0 x4, Clock 3 (SSD1) + # Despite the name, SSD2_CLKREQ# is used for SSD1 + register "PcieClkSrcUsage[3]" = "0x40" + register "PcieClkSrcClkReq[3]" = "3" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN# + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly) + register "srcclk_pin" = "3" # SSD2_CLKREQ# + device generic 0 on end + end + end + device ref north_xhci on # J_TYPEC1 + register "UsbTcPortEn" = "1" + register "TcssXhciEn" = "1" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tbt_dma0 on # J_TYPEC1 + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + + device ref south_xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2 + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port2 on end + end + end + end + end + device ref sata on + # SATA1 (SSD2) + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsEnableDitoConfig[1]" = "1" + register "SataSalpSupport" = "1" + end + device ref pcie_rp3 on + # PCIe root port #3 x1, Clock 1 (WLAN) + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieClkSrcUsage[1]" = "2" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[2]" = "1" + end + device ref pcie_rp6 on + # PCIe root port #6 x1, Clock 2 (CARD) + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[2]" = "5" + register "PcieClkSrcClkReq[2]" = "2" + end + device ref pcie_rp9 on + # PCIe root port #9 x4, Clock 0 (SSD2) + # Despite the name, SSD1_CLKREQ# is used for SSD2 + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[0]" = "8" + register "PcieClkSrcClkReq[0]" = "0" + register "PcieRpSlotImplemented[8]" = "1" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_DN# + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" # GPP_D13_RTD3 (labeled incorrectly) + register "srcclk_pin" = "0" + device generic 0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # J_TYPEC1 + use usb2_port3 as usb2_port + use tcss_usb3_port1 as usb3_port + # SBU & HSL follow CC + device generic 0 alias conn0 on end + end + end + end + end + end +end diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/romstage.c b/src/mainboard/system76/tgl-u/variants/lemp10/romstage.c new file mode 100644 index 0000000000..749efe668f --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/lemp10/romstage.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/util.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_MIXED, + .cbfs_index = 0, + .smbus = { + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} |