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-rw-r--r--src/mainboard/system76/gaze16/variants/gaze16-3050/gpio.c (renamed from src/mainboard/system76/gaze16/variants/gaze16-3050/include/variant/gpio.h)17
-rw-r--r--src/mainboard/system76/gaze16/variants/gaze16-3050/gpio_early.c17
-rw-r--r--src/mainboard/system76/gaze16/variants/gaze16-3060/gpio.c (renamed from src/mainboard/system76/gaze16/variants/gaze16-3060/include/variant/gpio.h)17
-rw-r--r--src/mainboard/system76/gaze16/variants/gaze16-3060/gpio_early.c17
4 files changed, 44 insertions, 24 deletions
diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3050/include/variant/gpio.h b/src/mainboard/system76/gaze16/variants/gaze16-3050/gpio.c
index a5e9b17f95..60b82de86f 100644
--- a/src/mainboard/system76/gaze16/variants/gaze16-3050/include/variant/gpio.h
+++ b/src/mainboard/system76/gaze16/variants/gaze16-3050/gpio.c
@@ -1,17 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
#include <soc/gpio.h>
-
-static const struct pad_config early_gpio_table[] = {
- PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
- PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
- PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
- PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
- PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
-};
+#include <variant/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
@@ -285,4 +275,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DAT_PCH
};
-#endif /* VARIANT_GPIO_H */
+void variant_configure_gpios(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3050/gpio_early.c b/src/mainboard/system76/gaze16/variants/gaze16-3050/gpio_early.c
new file mode 100644
index 0000000000..8c97e7f45e
--- /dev/null
+++ b/src/mainboard/system76/gaze16/variants/gaze16-3050/gpio_early.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+ PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
+ PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
+};
+
+void variant_configure_early_gpios(void)
+{
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3060/include/variant/gpio.h b/src/mainboard/system76/gaze16/variants/gaze16-3060/gpio.c
index f1d2cdabf5..ac14b64bf3 100644
--- a/src/mainboard/system76/gaze16/variants/gaze16-3060/include/variant/gpio.h
+++ b/src/mainboard/system76/gaze16/variants/gaze16-3060/gpio.c
@@ -1,17 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
#include <soc/gpio.h>
-
-static const struct pad_config early_gpio_table[] = {
- PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
- PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
- PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
- PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
- PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
-};
+#include <variant/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
@@ -285,4 +275,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_S7, NONE, DEEP), // MIC_DATA_PCH
};
-#endif /* VARIANT_GPIO_H */
+void variant_configure_gpios(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3060/gpio_early.c b/src/mainboard/system76/gaze16/variants/gaze16-3060/gpio_early.c
new file mode 100644
index 0000000000..8c97e7f45e
--- /dev/null
+++ b/src/mainboard/system76/gaze16/variants/gaze16-3060/gpio_early.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+ PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
+ PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
+};
+
+void variant_configure_early_gpios(void)
+{
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}