diff options
Diffstat (limited to 'src/mainboard/supermicro')
| -rw-r--r-- | src/mainboard/supermicro/x6dai_g/Config.lb | 34 | ||||
| -rw-r--r-- | src/mainboard/supermicro/x6dhe_g/Config.lb | 33 | ||||
| -rw-r--r-- | src/mainboard/supermicro/x6dhe_g2/Config.lb | 33 | ||||
| -rw-r--r-- | src/mainboard/supermicro/x6dhr_ig/Config.lb | 34 | ||||
| -rw-r--r-- | src/mainboard/supermicro/x6dhr_ig2/Config.lb | 34 |
5 files changed, 5 insertions, 163 deletions
diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb index 003e74b1e0..3fca8b51a1 100644 --- a/src/mainboard/supermicro/x6dai_g/Config.lb +++ b/src/mainboard/supermicro/x6dai_g/Config.lb @@ -3,39 +3,7 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +include /config/nofailovercalculation128.lb ## ## Set all of the defaults for an x86 architecture diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb index 756ed4472b..c2efe3f90c 100644 --- a/src/mainboard/supermicro/x6dhe_g/Config.lb +++ b/src/mainboard/supermicro/x6dhe_g/Config.lb @@ -3,39 +3,8 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) +include /config/nofailovercalculation128.lb -## -## Compute a range of ROM that can be cached to speed up coreboot. -## execution speed. -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb index 2b88e344a7..c014050fc4 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Config.lb +++ b/src/mainboard/supermicro/x6dhe_g2/Config.lb @@ -3,39 +3,8 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) +include /config/nofailovercalculation128.lb -## -## Compute a range of ROM that can be cached to speed up coreboot. -## execution speed. -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb index 5b83ab5ea4..048dc63613 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Config.lb +++ b/src/mainboard/supermicro/x6dhr_ig/Config.lb @@ -3,39 +3,7 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +include /config/nofailovercalculation128.lb ## ## Set all of the defaults for an x86 architecture diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb index 61204b73df..58f3835dbb 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Config.lb +++ b/src/mainboard/supermicro/x6dhr_ig2/Config.lb @@ -3,39 +3,7 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +include /config/nofailovercalculation128.lb ## ## Set all of the defaults for an x86 architecture |