3 files changed, 0 insertions, 520 deletions
diff --git a/src/mainboard/supermicro/h8qgi/acpi/routing.asl b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
deleted file mode 100644
index 085c28f737..0000000000
--- a/src/mainboard/supermicro/h8qgi/acpi/routing.asl
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - SR5650 HT */
-		Package() { 0xFFFF, Zero, INTA, Zero },
-
-		/* Bus 0, Dev 1 - CLKCONFIG */
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
-		Package() {0x0002FFFF, 0, INTE, 0 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package() {0x0004FFFF, 0, INTE, 0 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
-		/* Bus 0, Dev 9 - PCIe Bridge */
-
-		/* Bus 0, Dev a - PCIe Bridge */
-
-		/* Bus 0, Dev b - PCIe Bridge */
-		Package() {0x000BFFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev c - PCIe Bridge */
-		Package() {0x000CFFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev d - PCIe Bridge for Intel 82576 Giga NIC*/
-		Package() {0x000DFFFF, 0, INTG, 0 },
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package() {0x0011FFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package() {0x0012FFFF, 0, INTA, 0 },
-		Package() {0x0012FFFF, 1, INTB, 0 },
-		Package() {0x0012FFFF, 2, INTC, 0 },
-		Package() {0x0012FFFF, 3, INTD, 0 },
-
-		Package() {0x0013FFFF, 0, INTC, 0 },
-		Package() {0x0013FFFF, 1, INTD, 0 },
-		Package() {0x0013FFFF, 2, INTA, 0 },
-		Package() {0x0013FFFF, 2, INTB, 0 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - SR5650 HT */
-		Package() { 0xFFFF, Zero, Zero, 55 },
-
-		/* Bus 0, Dev 1 - CLKCONFIG */
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot (GFX0) */
-		Package() {0x0002FFFF, 0, 0, 0x34 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package() {0x0004FFFF, 0, 0, 0x34 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-
-		/* Bus 0, Dev 7 - PCIe Bridge */
-
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
-		/* Bus 0, Dev 9 - PCIe Bridge */
-
-		/* Bus 0, Dev A - PCIe Bridge */
-
-		/* Bus 0, Dev B - PCIe Bridge */
-		Package() {0x000BFFFF, 0, 0, 0x36 },
-
-		/* Bus 0, Dev C - PCIe Bridge */
-		Package() {0x000CFFFF, 0, 0, 0x36 },
-
-		/* Bus 0, Dev D - PCIe Bridge For Intel 82576 Giga NIC*/
-		Package() {0x000DFFFF, 0, 0, 0x36 },
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package() {0x0011FFFF, 0, 0, 0x16 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package( ){0x0012FFFF, 0, 0, 16 },
-		Package() {0x0012FFFF, 1, 0, 17 },
-		Package() {0x0012FFFF, 2, 0, 18 },
-		Package() {0x0012FFFF, 3, 0, 19 },
-
-		Package() {0x0013FFFF, 0, 0, 18 },
-		Package() {0x0013FFFF, 1, 0, 19 },
-		Package() {0x0013FFFF, 2, 0, 16 },
-		Package() {0x0013FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package() {0x0014FFFF, 0, 0, 16 },
-		Package() {0x0014FFFF, 1, 0, 17 },
-		Package() {0x0014FFFF, 2, 0, 18 },
-		Package() {0x0014FFFF, 3, 0, 19 },
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 4 */
-		Package() {0x0000FFFF, 0, INTC, 0 },
-		Package() {0x0000FFFF, 1, INTD, 0 },
-		Package() {0x0000FFFF, 2, INTA, 0 },
-		Package() {0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 0x18 },
-		Package(){0x0000FFFF, 1, 0, 0x19 },
-		Package(){0x0000FFFF, 2, 0, 0x1A },
-		Package(){0x0000FFFF, 3, 0, 0x1B },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 0x2C },
-		Package(){0x0000FFFF, 1, 0, 0x2D },
-		Package(){0x0000FFFF, 2, 0, 0x2E },
-		Package(){0x0000FFFF, 3, 0, 0x2F },
-	})
-
-	Name(PSb, Package(){
-		/* PCIe slot - Hooked to PCIe slot 11 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSb, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 0x20 },
-		Package(){0x0000FFFF, 1, 0, 0x21 },
-		Package(){0x0000FFFF, 2, 0, 0x22 },
-		Package(){0x0000FFFF, 3, 0, 0x23 },
-	})
-
-	Name(PSc, Package(){
-		/* PCIe slot - Hooked to PCIe slot 12 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APSc, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 0x24 },
-		Package(){0x0000FFFF, 1, 0, 0x25 },
-		Package(){0x0000FFFF, 2, 0, 0x26 },
-		Package(){0x0000FFFF, 3, 0, 0x27 },
-	})
-
-	Name(PSd, Package(){
-		/* PCIe slot - Hooked to PCIe slot 13 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APSd, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 0x28 },
-		Package(){0x0000FFFF, 1, 0, 0x29 },
-		Package(){0x0000FFFF, 2, 0, 0x2A },
-		Package(){0x0000FFFF, 3, 0, 0x2B },
-	})
-}
diff --git a/src/mainboard/supermicro/h8qgi/acpi/sata.asl b/src/mainboard/supermicro/h8qgi/acpi/sata.asl
deleted file mode 100644
index 9e0e535da6..0000000000
--- a/src/mainboard/supermicro/h8qgi/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P0IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P1IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P2IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P3IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (LGreater(\_SB.P0IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P0PR)
-		}
-
-		if (\_SB.P1PR) {
-			if (LGreater(\_SB.P1IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P1PR)
-		}
-
-		if (\_SB.P2PR) {
-			if (LGreater(\_SB.P2IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P2PR)
-		}
-
-		if (\_SB.P3PR) {
-			if (LGreater(\_SB.P3IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P3PR)
-		}
-	}
-}
diff --git a/src/mainboard/supermicro/h8qgi/acpi/usb.asl b/src/mainboard/supermicro/h8qgi/acpi/usb.asl
deleted file mode 100644
index 0f8ca9c0ab..0000000000
--- a/src/mainboard/supermicro/h8qgi/acpi/usb.asl
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "usb.asl"
-	}
-*/
-Method(UCOC, 0) {
-	Sleep(20)
-	Store(0x13,CMTI)
-	Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if(LEqual(GPB0,PLC0)) {
-				Not(PLC0,PLC0)
-				Store(PLC0, \_SB.PT0D)
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (LEqual(GPB1,PLC1)) {
-				Not(PLC1,PLC1)
-				Store(PLC1, \_SB.PT1D)
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (LEqual(GPB2,PLC2)) {
-				Not(PLC2,PLC2)
-				Store(PLC2, \_SB.PT2D)
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (LEqual(GPB3,PLC3)) {
-				Not(PLC3,PLC3)
-				Store(PLC3, \_SB.PT3D)
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (LEqual(GPB4,PLC4)) {
-				Not(PLC4,PLC4)
-				Store(PLC4, \_SB.PT4D)
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (LEqual(GPB5,PLC5)) {
-				Not(PLC5,PLC5)
-				Store(PLC5, \_SB.PT5D)
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (LEqual(GPB6,PLC6)) {
-				Not(PLC6,PLC6)
-				Store(PLC6, \_SB.PT6D)
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (LEqual(GPB7,PLC7)) {
-				Not(PLC7,PLC7)
-				Store(PLC7, \_SB.PT7D)
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (LEqual(G8IS,PLC8)) {
-				Not(PLC8,PLC8)
-				Store(PLC8, \_SB.PT8D)
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (LEqual(G9IS,0)) {
-			Store(1,\_SB.PT9D)
-			}
-		}
-	}
-}