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Diffstat (limited to 'src/mainboard/supermicro/h8dme')
-rw-r--r--src/mainboard/supermicro/h8dme/romstage.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index ac441a6ec8..4b08206a0f 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -52,7 +52,6 @@
// for enable the FAN
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
-#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
@@ -64,15 +63,11 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@@ -191,8 +186,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
-#endif
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -225,8 +218,6 @@ static void sio_setup(void)
#define RC0 (2<<8)
#define RC1 (1<<8)
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* The SPD is being read from the CPU1 (marked CPU2 on the board) and we
@@ -371,4 +362,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
-#endif