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Diffstat (limited to 'src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi')
-rw-r--r--src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi363
1 files changed, 0 insertions, 363 deletions
diff --git a/src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi b/src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi
deleted file mode 100644
index 823240cab0..0000000000
--- a/src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi
+++ /dev/null
@@ -1,363 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/dts-v1/;
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "sifive,fu740-c000", "sifive,fu740";
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- ethernet0 = &eth0;
- };
-
- chosen {
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu0: cpu@0 {
- compatible = "sifive,bullet0", "riscv";
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <16384>;
- next-level-cache = <&ccache>;
- reg = <0x0>;
- riscv,isa = "rv64imac";
- // the S7 core does not support Supervisor mode and has no FPU
- status = "disabled";
- cpu0_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu1: cpu@1 {
- compatible = "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <40>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <40>;
- mmu-type = "riscv,sv39";
- next-level-cache = <&ccache>;
- reg = <0x1>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- cpu1_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu2: cpu@2 {
- compatible = "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <40>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <40>;
- mmu-type = "riscv,sv39";
- next-level-cache = <&ccache>;
- reg = <0x2>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- cpu2_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu3: cpu@3 {
- compatible = "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <40>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <40>;
- mmu-type = "riscv,sv39";
- next-level-cache = <&ccache>;
- reg = <0x3>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- cpu3_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu4: cpu@4 {
- compatible = "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <40>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <40>;
- mmu-type = "riscv,sv39";
- next-level-cache = <&ccache>;
- reg = <0x4>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- cpu4_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
-
- core1 {
- cpu = <&cpu1>;
- };
-
- core2 {
- cpu = <&cpu2>;
- };
-
- core3 {
- cpu = <&cpu3>;
- };
-
- core4 {
- cpu = <&cpu4>;
- };
- };
- };
- };
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- ranges;
- // clint is mainly used by openSBI and not the OS, since interrupts-extended currently only
- // contains machine mode interrupts which the OS will ignore if not running in machine mode
- clint: clint@2000000 {
- compatible = "riscv,clint0";
- //TODO Add RISCV_M_SOFT_IRQ and RISCV_M_TIME_IRQ macros for better readability
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
- &cpu1_intc 3 &cpu1_intc 7
- &cpu2_intc 3 &cpu2_intc 7
- &cpu3_intc 3 &cpu3_intc 7
- &cpu4_intc 3 &cpu4_intc 7>;
- reg = <0x0 0x2000000 0x0 0x10000>;
- };
- plic0: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
- reg = <0x0 0xc000000 0x0 0x4000000>;
- riscv,ndev = <69>;
- interrupt-controller;
- interrupts-extended =
- <&cpu0_intc 0xffffffff>,
- <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
- <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
- <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
- <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
- };
- prci: clock-controller@10000000 {
- compatible = "sifive,fu740-c000-prci";
- reg = <0x0 0x10000000 0x0 0x1000>;
- clocks = <&hfclk>, <&rtcclk>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
- uart0: serial@10010000 {
- compatible = "sifive,fu740-c000-uart", "sifive,uart0";
- reg = <0x0 0x10010000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <39>;
- clocks = <&prci 7>;
- status = "disabled";
- };
- uart1: serial@10011000 {
- compatible = "sifive,fu740-c000-uart", "sifive,uart0";
- reg = <0x0 0x10011000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <40>;
- clocks = <&prci 7>;
- status = "disabled";
- };
- i2c0: i2c@10030000 {
- compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
- reg = <0x0 0x10030000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <52>;
- clocks = <&prci 7>;
- reg-shift = <2>;
- reg-io-width = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- i2c1: i2c@10031000 {
- compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
- reg = <0x0 0x10031000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <53>;
- clocks = <&prci 7>;
- reg-shift = <2>;
- reg-io-width = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- qspi0: spi@10040000 {
- compatible = "sifive,fu740-c000-spi", "sifive,spi0";
- reg = <0x0 0x10040000 0x0 0x1000>,
- <0x0 0x20000000 0x0 0x10000000>;
- interrupt-parent = <&plic0>;
- interrupts = <41>;
- clocks = <&prci 7>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- qspi1: spi@10041000 {
- compatible = "sifive,fu740-c000-spi", "sifive,spi0";
- reg = <0x0 0x10041000 0x0 0x1000>,
- <0x0 0x30000000 0x0 0x10000000>;
- interrupt-parent = <&plic0>;
- interrupts = <42>;
- clocks = <&prci 7>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- spi0: spi@10050000 {
- compatible = "sifive,fu740-c000-spi", "sifive,spi0";
- reg = <0x0 0x10050000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <43>;
- clocks = <&prci 7>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- eth0: ethernet@10090000 {
- compatible = "sifive,fu540-c000-gem";
- interrupt-parent = <&plic0>;
- interrupts = <55>;
- reg = <0x0 0x10090000 0x0 0x2000>,
- <0x0 0x100a0000 0x0 0x1000>;
- local-mac-address = [00 00 00 00 00 00];
- clock-names = "pclk", "hclk";
- clocks = <&prci 2>,
- <&prci 2>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- phandle = <0x13>; //TODO remove
- };
- pwm0: pwm@10020000 {
- compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
- reg = <0x0 0x10020000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <44>, <45>, <46>, <47>;
- clocks = <&prci 7>;
- #pwm-cells = <3>;
- status = "disabled";
- };
- pwm1: pwm@10021000 {
- compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
- reg = <0x0 0x10021000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <48>, <49>, <50>, <51>;
- clocks = <&prci 7>;
- #pwm-cells = <3>;
- status = "disabled";
- };
- ccache: cache-controller@2010000 {
- compatible = "sifive,fu740-c000-ccache", "cache";
- cache-block-size = <64>;
- cache-level = <2>;
- cache-sets = <2048>;
- cache-size = <2097152>;
- cache-unified;
- interrupt-parent = <&plic0>;
- interrupts = <19>, <21>, <22>, <20>;
- reg = <0x0 0x2010000 0x0 0x1000>;
- };
- gpio: gpio@10060000 {
- compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
- interrupt-parent = <&plic0>;
- interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
- <30>, <31>, <32>, <33>, <34>, <35>, <36>,
- <37>, <38>;
- reg = <0x0 0x10060000 0x0 0x1000>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&prci 7>;
- status = "disabled";
- };
- pcie@e00000000 {
- compatible = "sifive,fu740-pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- reg = <0xe 0x00000000 0x0 0x80000000>,
- <0xd 0xf0000000 0x0 0x10000000>,
- <0x0 0x100d0000 0x0 0x1000>;
- reg-names = "dbi", "config", "mgmt";
- device_type = "pci";
- dma-coherent;
- bus-range = <0x0 0xff>;
- //TODO
- //ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
- // <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
- // <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
- // <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
- ranges = <0x81000000 0x00 0x60080000 0x00 0x60080000 0x00 0x10000 0x82000000 0x00 0x60090000 0x00 0x60090000 0x00 0xff70000 0x82000000 0x00 0x70000000 0x00 0x70000000 0x00 0x10000000 0xc3000000 0x20 0x00 0x20 0x00 0x20 0x00>;
- num-lanes = <0x8>;
- interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
- interrupt-names = "msi", "inta", "intb", "intc", "intd";
- interrupt-parent = <&plic0>;
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
- <0x0 0x0 0x0 0x2 &plic0 58>,
- <0x0 0x0 0x0 0x3 &plic0 59>,
- <0x0 0x0 0x0 0x4 &plic0 60>;
- clock-names = "pcie_aux";
- clocks = <&prci 8>;
- pwren-gpios = <&gpio 5 0>;
- reset-gpios = <&gpio 8 0>;
- resets = <&prci 4>;
- status = "okay";
- };
- };
-};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 11:58:42 +0000