diff options
Diffstat (limited to 'src/mainboard/siemens/mc_ehl')
5 files changed, 105 insertions, 3 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig index 1ad4ede557..151d24a49c 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig @@ -2,6 +2,7 @@ if BOARD_SIEMENS_MC_EHL5 config BOARD_SPECIFIC_OPTIONS def_bool y + select DRIVERS_I2C_PTN3460 select DRIVERS_I2C_RV3028C7 select DRIVER_INTEL_I210 select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc index 6e87f9fc1a..be8ec05805 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc @@ -3,4 +3,5 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += lcd_panel.c ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb index f14c225a0b..53ea1f6e6b 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb @@ -106,6 +106,9 @@ chip soc/intel/elkhartlake register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE" register "pse_tsn_phy_irq_edge[1]" = "RISING_EDGE" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "1" + register "common_soc_config" = "{ .i2c[1] = { .speed = I2C_SPEED_STANDARD, @@ -158,12 +161,16 @@ chip soc/intel/elkhartlake end end device pci 15.2 on # I2C2 - # Add dummy I2C device to limit BUS speed to 100 kHz in OS + # Add dummy I2C device to limit BUS speed to 100 kHz in OS chip drivers/i2c/generic register "hid" = ""PRP0001"" register "speed" = "I2C_SPEED_STANDARD" device i2c 0x7f on end end + # Enable external display bridge (eDP to LVDS) + chip drivers/i2c/ptn3460 + device i2c 0x20 on end # PTN3460 DP2LVDS Bridge + end end device pci 15.3 on end # I2C3 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c index 20a89c64d1..e57152fc79 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c @@ -133,8 +133,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), /* M.2_SSD_SATA_DEVSLP_1 */ PAD_NC(GPP_E15, NONE), /* Not connected */ PAD_NC(GPP_E16, NONE), /* Not connected */ - PAD_NC(GPP_E18, NONE), /* Not connected */ - PAD_NC(GPP_E19, NONE), /* Not connected */ PAD_NC(GPP_E23, NONE), /* Not connected */ /* Community 5 - GpioGroup GPP_R */ diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c new file mode 100644 index 0000000000..0b68ed7e86 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> +#include <drivers/i2c/ptn3460/ptn3460.h> +#include <hwilib.h> +#include <types.h> + +/** \brief This function provides EDID data to the driver for DP2LVDS Bridge (PTN3460). + * @param edid_data pointer to EDID data in driver + * @return CB_SUCCESS on successful EDID data retrieval, CB_ERR otherwise + */ +enum cb_err mainboard_ptn3460_get_edid(uint8_t edid_data[PTN_EDID_LEN]) +{ + const char *hwi_block = "hwinfo.hex"; + + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return CB_ERR; + } + + /* Get EDID data from hwinfo block */ + if (hwilib_get_field(Edid, edid_data, PTN_EDID_LEN) != PTN_EDID_LEN) { + printk(BIOS_ERR, "LCD: No EDID data available in %s\n", hwi_block); + return CB_ERR; + } + return CB_SUCCESS; +} + +/** \brief This function provides EDID block [0..6] to the driver for DP2LVDS Bridge (PTN3460) + * which has to be used. + * @return Index of the EDID slot selected for EDID emulation + */ +uint8_t mainboard_ptn3460_select_edid_table(void) +{ + return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ +} + +/** \brief Function to enable mainboard to adjust the config data of PTN3460. For reference, + * see NXP document AN11128 - PTN3460 Programming guide. + * @param *cfg_ptr Pointer to the PTN config structure to modify + * @return CB_SUCCESS if data was modified and needs to be updated; CB_ERR on error + */ +enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg) +{ + const char *hwi_block = "hwinfo.hex"; + uint8_t disp_con = 0, color_depth = 0; + + /* Get display-specific configuration from hwinfo. */ + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return CB_ERR; + } + if (hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != sizeof(disp_con)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return CB_ERR; + } + if (hwilib_get_field(PF_Color_Depth, &color_depth, + sizeof(color_depth)) != sizeof(color_depth)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return CB_ERR; + } + + /* Set up PTN3460 registers based on hwinfo and fixed board-specific parameters: */ + /* Use 2 lanes for eDP, no P/N swapping, no ASSR, allow both HBR and RBR modes. */ + cfg->dp_interface_ctrl = 0x00; + /* Use odd bus for LVDS clock distribution only. */ + cfg->lvds_interface_ctrl1 = 0x01; + if (disp_con == PF_DISPLCON_LVDS_DUAL) { + /* Turn on dual LVDS lane and clock. */ + cfg->lvds_interface_ctrl1 |= 0x0b; + } + if (color_depth == PF_COLOR_DEPTH_6BIT) { + /* Use 18 bits per pixel. */ + cfg->lvds_interface_ctrl1 |= 0x20; + } + /* No LVDS clock spreading, 300 mV LVDS swing */ + cfg->lvds_interface_ctrl2 = 0x03; + /* No LVDS lane/channel swapping */ + cfg->lvds_interface_ctrl3 = 0x00; + /* Enable VDD to LVDS active delay. */ + cfg->t2_delay = 0x01; + /* LVDS to backlight active delay: 200 ms */ + cfg->t3_timing = 0x04; + /* Minimum re-power delay: 500 ms */ + cfg->t12_timing = 0x0a; + /* Backlight off to LVDS inactive delay: 200 ms */ + cfg->t4_timing = 0x04; + /* Enable LVDS to VDD inactive delay. */ + cfg->t5_delay = 0x01; + /* Enable backlight control. */ + cfg->backlight_ctrl = 0x00; + + return CB_SUCCESS; +} |