diff options
Diffstat (limited to 'src/mainboard/purism')
3 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 4f34f7d6d4..0d0fc720f7 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -24,7 +24,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # EC host command ranges are in 0x380-0x383 & 0x80-0x8f register "gen1_dec" = "0x00000381" register "gen2_dec" = "0x000c0081" @@ -57,6 +57,6 @@ chip soc/intel/broadwell device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus device pci 1f.6 off end # Thermal -# end + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index 237e6979ec..256077cbd9 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # Port 0 is HDD # Port 3 is M.2 NGFF register "sata_port_map" = "0x9" @@ -11,6 +11,6 @@ chip soc/intel/broadwell register "sata_port3_gen3_dtle" = "9" device pci 1c.2 on end # PCIe Port #3 - LAN -# end + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index b9b29cd6ff..d88c19c26a 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # Port 0 is HDD # Port 1 is M.2 NGFF register "sata_port_map" = "0x3" @@ -11,6 +11,6 @@ chip soc/intel/broadwell register "sata_port1_gen3_dtle" = "9" device pci 1d.0 on end # USB2 EHCI -# end + end end end |