diff options
Diffstat (limited to 'src/mainboard/purism/librem_whl')
| -rw-r--r-- | src/mainboard/purism/librem_whl/Kconfig | 62 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/Kconfig.name | 3 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/Makefile.inc | 7 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/acpi/mainboard.asl | 16 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/board_info.txt | 8 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/devicetree.cb | 305 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/dsdt.asl | 26 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/ramstage.c | 13 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/romstage.c | 59 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt | bin | 4608 -> 0 bytes | |||
| -rw-r--r-- | src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c | 791 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c | 33 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h | 11 |
13 files changed, 0 insertions, 1334 deletions
diff --git a/src/mainboard/purism/librem_whl/Kconfig b/src/mainboard/purism/librem_whl/Kconfig deleted file mode 100644 index bc25fb5b3b..0000000000 --- a/src/mainboard/purism/librem_whl/Kconfig +++ /dev/null @@ -1,62 +0,0 @@ -config BOARD_PURISM_BASEBOARD_LIBREM_WHL - def_bool n - select BOARD_ROMSIZE_KB_16384 - select DRIVERS_GENERIC_CBFS_SERIAL - select DRIVERS_USB_ACPI - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select INTEL_GMA_HAVE_VBT - select NO_UART_ON_SUPERIO - select SOC_INTEL_COMMON_BLOCK_HDA - select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SOC_INTEL_WHISKEYLAKE - select SPD_READ_BY_WORD - select USE_LEGACY_8254_TIMER - -if BOARD_PURISM_BASEBOARD_LIBREM_WHL - -config MAINBOARD_DIR - string - default "purism/librem_whl" - -config MAINBOARD_FAMILY - string - default "Librem Mini" if BOARD_PURISM_LIBREM_MINI - -config MAINBOARD_PART_NUMBER - string - default "Librem Mini" if BOARD_PURISM_LIBREM_MINI - -config VARIANT_DIR - string - default "librem_mini" if BOARD_PURISM_LIBREM_MINI - -config CBFS_SIZE - hex - default 0x800000 - -config MAX_CPUS - int - default 8 - -config DIMM_MAX - int - default 2 - -config DIMM_SPD_SIZE - int - default 512 - -config VGA_BIOS_ID - string - default "8086,3ea0" - -config PXE_ROM_ID - string - default "10ec,8168" - -# This platform has limited means to display POST codes -config NO_POST - default y - -endif diff --git a/src/mainboard/purism/librem_whl/Kconfig.name b/src/mainboard/purism/librem_whl/Kconfig.name deleted file mode 100644 index 41a4003102..0000000000 --- a/src/mainboard/purism/librem_whl/Kconfig.name +++ /dev/null @@ -1,3 +0,0 @@ -config BOARD_PURISM_LIBREM_MINI - bool "Librem Mini" - select BOARD_PURISM_BASEBOARD_LIBREM_WHL diff --git a/src/mainboard/purism/librem_whl/Makefile.inc b/src/mainboard/purism/librem_whl/Makefile.inc deleted file mode 100644 index ba157dfd05..0000000000 --- a/src/mainboard/purism/librem_whl/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-y += variants/$(VARIANT_DIR)/gpio.c -ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c -ramstage-y += ramstage.c - -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/purism/librem_whl/acpi/mainboard.asl b/src/mainboard/purism/librem_whl/acpi/mainboard.asl deleted file mode 100644 index 0c9a76b168..0000000000 --- a/src/mainboard/purism/librem_whl/acpi/mainboard.asl +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.LPCB) -{ - Device (AC) - { - Name (_HID, "ACPI0003") - Name (_PCL, Package () { LPCB }) - Name (ACFG, One) - - Method (_PSR, 0, NotSerialized) - { - Return (ACFG) - } - } -} diff --git a/src/mainboard/purism/librem_whl/board_info.txt b/src/mainboard/purism/librem_whl/board_info.txt deleted file mode 100644 index e72dcdf2b7..0000000000 --- a/src/mainboard/purism/librem_whl/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Vendor name: Purism -Board name: librem_whl -Category: desktop -Release year: 2020 -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb deleted file mode 100644 index 205033230b..0000000000 --- a/src/mainboard/purism/librem_whl/devicetree.cb +++ /dev/null @@ -1,305 +0,0 @@ -chip soc/intel/cannonlake - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - -# ACPI (soc/intel/cannonlake/acpi.c) - # Disable s0ix - register "s0ix_enable" = "0" - - # PM Timer Enabled - register "PmTimerDisabled" = "0" - - # Disable DPTF - register "dptf_enable" = "0" - -# CPU (soc/intel/cannonlake/cpu.c) - # Power limit - register "power_limits_config" = "{ - .tdp_pl1_override = 25, - .tdp_pl2_override = 28, - }" - - # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - -# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" - -# FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # Serial I/O - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexSPI1] = PchSerialIoDisabled, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoDisabled, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # SATA - register "SataMode" = "Sata_AHCI" - register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "1" # 2.5" - register "SataPortsEnable[2]" = "1" # m.2 - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[2]" = "0" - - # Audio - register "PchHdaDspEnable" = "0" - register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkDmic0" = "0" - register "PchHdaAudioLinkDmic1" = "0" - register "PchHdaAudioLinkSsp0" = "0" - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkSsp2" = "0" - register "PchHdaAudioLinkSndw1" = "0" - register "PchHdaAudioLinkSndw2" = "0" - register "PchHdaAudioLinkSndw3" = "0" - register "PchHdaAudioLinkSndw4" = "0" - - # USB - register "SsicPortEnable" = "0" - - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper - register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth - register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower - - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper - - # All SRCCLKREQ pins mapped directly - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # Set all SRCCLKREQ pins as free-use - register "PcieClkSrcUsage[0]" = "0x80" - register "PcieClkSrcUsage[1]" = "0x80" - register "PcieClkSrcUsage[2]" = "0x80" - register "PcieClkSrcUsage[3]" = "0x80" - register "PcieClkSrcUsage[4]" = "0x80" - register "PcieClkSrcUsage[5]" = "0x80" - - # PCI Express Root Port #8 x1, Clock 2 (WLAN) - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - - # PCI Express Root Port #10 x1, Clock 3 (LAN) - register "PcieRpEnable[9]" = "1" - register "PcieRpLtrEnable[9]" = "0" - - # PCI Express Root port #13 x4, Clock 1 (NVMe) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - - # Misc - register "AcousticNoiseMitigation" = "1" - register "satapwroptimize" = "1" - - # Power - register "PchPmSlpS3MinAssert" = "3" # 50ms - register "PchPmSlpS4MinAssert" = "1" # 1s - register "PchPmSlpSusMinAssert" = "2" # 500ms - register "PchPmSlpAMinAssert" = "4" # 2s - - # Thermal - register "tcc_offset" = "12" - - # Serial IRQ Mode - register "serirq_mode" = "SERIRQ_CONTINUOUS" - -# PMC (soc/intel/cannonlake/pmc.c) - # Disable deep Sx states - register "deep_sx_config" = "0" - -# PM Util (soc/intel/cannonlake/pmutil.c) - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) - register "gpe0_dw0" = "PMC_GPP_C" - register "gpe0_dw1" = "PMC_GPP_D" - register "gpe0_dw2" = "PMC_GPP_E" - -# Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end - device pci 12.0 on end # Thermal Subsystem - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on # USB xHCI - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left Upper"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left Lower"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Upper"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right Lower"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right Upper"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 3)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - device usb 2.7 off end - end - chip drivers/usb/acpi - device usb 2.8 off end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Lower"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left Upper"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left Lower"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - device usb 3.2 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Lower"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Upper"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.5 on end - end - end - end - end - device pci 14.1 off end # USB xDCI (OTG) - device pci 15.0 off end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 off # Management Engine Interface 1 - # HECI must be enabled w/HAP disable else S3 issues - register "HeciEnabled" = "1" - end - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 (WLAN) - register "PcieRpSlotImplemented[7]" = "1" - end - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 on # PCI Express Port 10 (LAN) - register "PcieRpSlotImplemented[9]" = "1" - end - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 (NVMe) - register "PcieRpSlotImplemented[12]" = "1" - end - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on end # LPC Bridge - device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/purism/librem_whl/dsdt.asl b/src/mainboard/purism/librem_whl/dsdt.asl deleted file mode 100644 index 567a8c01d1..0000000000 --- a/src/mainboard/purism/librem_whl/dsdt.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 /* OEM revision */ -) -{ - #include <soc/intel/common/block/acpi/acpi/platform.asl> - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> - #include <cpu/intel/common/acpi/cpu.asl> - - Device (\_SB.PCI0) - { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/cannonlake/acpi/southbridge.asl> - } - - #include <southbridge/intel/common/acpi/sleepstates.asl> - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_whl/ramstage.c deleted file mode 100644 index 56ed1b7844..0000000000 --- a/src/mainboard/purism/librem_whl/ramstage.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/ramstage.h> -#include <variant/gpio.h> - -void mainboard_silicon_init_params(FSP_S_CONFIG *params) -{ - /* Configure pads prior to SiliconInit() in case there's any - * dependencies during hardware initialization. */ - size_t num_gpios; - const struct pad_config *gpio_table = variant_gpio_table(&num_gpios); - cnl_configure_pads(gpio_table, num_gpios); -} diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_whl/romstage.c deleted file mode 100644 index 3a3ca6b491..0000000000 --- a/src/mainboard/purism/librem_whl/romstage.c +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/cnl_memcfg_init.h> -#include <soc/romstage.h> - -static const struct cnl_mb_cfg memcfg = { - - /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ - .spd[0] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa0}, - }, - .spd[1] = {.read_type = NOT_EXISTING}, - .spd[2] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa4}, - }, - .spd[3] = {.read_type = NOT_EXISTING}, - - /* - * Rcomp resistor values. These values represent the resistance in - * ohms of the three rcomp resistors attached to the DDR_COMP_0, - * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. - */ - .rcomp_resistor = { 121, 81, 100 }, - - /* Rcomp target values */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, - - /* - * Indicates whether memory is interleaved. - * Set to 1 for an interleaved design, - * set to 0 for non-interleaved design. - */ - .dq_pins_interleaved = 1, - - /* - * VREF_CA configuration. - * Set to 0 VREF_CA goes to both CH_A and CH_B, - * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, - * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. - */ - .vref_ca_config = 2, - - /* Early Command Training */ - .ect = 0, -}; - -void mainboard_memory_init_params(FSPM_UPD *memupd) -{ - FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; - cannonlake_memcfg_init(mem_cfg, &memcfg); - - /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ - mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; - mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; - mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 2; - mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; -} diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt b/src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt Binary files differdeleted file mode 100644 index 2e657d1a9f..0000000000 --- a/src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt +++ /dev/null diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c deleted file mode 100644 index 254510ead5..0000000000 --- a/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c +++ /dev/null @@ -1,791 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <variant/gpio.h> - -/* Pad configuration was generated automatically using intelp2m utility */ -static const struct pad_config gpio_table[] = { - - /* ------- GPIO Community 0 ------- */ - - /* ------- GPIO Group GPP_A ------- */ - - /* GPP_A0 - RCIN# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), - - /* GPP_A1 - LAD0 */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), - - /* GPP_A2 - LAD1 */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), - - /* GPP_A3 - LAD2 */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), - - /* GPP_A4 - LAD3 */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), - - /* GPP_A5 - LFRAME# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - - /* GPP_A6 - SERIRQ */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - - /* GPP_A7 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_A7, 0, DEEP), - - /* GPP_A8 - CLKRUN# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - - /* GPP_A9 - CLKOUT_LPC0 */ - /* DW0: 0x44000700, DW1: 0x00001000 */ - PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), - - /* GPP_A10 - CLKOUT_LPC1 */ - /* DW0: 0x44000700, DW1: 0x00001000 */ - PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), - - /* GPP_A11 - GPIO */ - /* DW0: 0x80880201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_A11, 1, PLTRST), - - /* GPP_A12 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_A12, 1, PLTRST), - - /* GPP_A13 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_A13, 1, PLTRST), - - /* GPP_A14 - SUS_STAT# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - - /* GPP_A15 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_A15, 1, PLTRST), - - /* GPP_A16 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00003000 */ - PAD_CFG_TERM_GPO(GPP_A16, 0, UP_20K, PLTRST), - - /* GPP_A17 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_A17, 1, PLTRST), - - /* GPP_A18 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ - PAD_NC(GPP_A18, UP_20K), - - /* GPP_A19 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ - PAD_NC(GPP_A19, UP_20K), - - /* GPP_A20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ - PAD_NC(GPP_A20, UP_20K), - - /* GPP_A21 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ - PAD_NC(GPP_A21, UP_20K), - - /* GPP_A22 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ - PAD_NC(GPP_A22, UP_20K), - - /* GPP_A23 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ - PAD_NC(GPP_A23, UP_20K), - - /* ------- GPIO Group GPP_B ------- */ - - /* GPP_B0 - Reserved */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), - - /* GPP_B1 - Reserved */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - - /* GPP_B2 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_B2, 1, PLTRST), - - /* GPP_B3 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_B3, 1, PLTRST), - - /* GPP_B4 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), - - /* GPP_B5 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_B5, NONE), - - /* GPP_B6 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_B6, NONE), - - /* GPP_B7 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_B7, NONE), - - /* GPP_B8 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_B8, NONE), - - /* GPP_B9 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_B9, NONE), - - /* GPP_B10 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_B10, NONE), - - /* GPP_B11 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_B11, 1, PLTRST), - - /* GPP_B12 - SLP_S0# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - - /* GPP_B13 - PLTRST# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - - /* GPP_B14 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_B14, 1, PLTRST), - - /* GPP_B15 - GSPI0_CS0# */ - /* DW0: 0x00000701, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B15, NONE, PWROK, NF1), - - /* GPP_B16 - GSPI0_CLK */ - /* DW0: 0x84000601, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF1), - - /* GPP_B17 - GSPI0_MISO */ - /* DW0: 0x44000502, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - - /* GPP_B18 - GSPI0_MOSI */ - /* DW0: 0x84000601, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1), - - /* GPP_B19 - GSPI1_CS0# */ - /* DW0: 0x84000400, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B19, NONE, PLTRST, NF1), - - /* GPP_B20 - GSPI1_CLK */ - /* DW0: 0x84000400, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B20, NONE, PLTRST, NF1), - - /* GPP_B21 - GSPI1_MISO */ - /* DW0: 0x84000402, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B21, NONE, PLTRST, NF1), - - /* GPP_B22 - GSPI1_MOSI */ - /* DW0: 0x84000400, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1), - - /* GPP_B23 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_B23, 1, DEEP), - - /* ------- GPIO Group GPP_G ------- */ - - /* GPP_G0 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00001000 */ - PAD_CFG_TERM_GPO(GPP_G0, 0, DN_20K, PWROK), - - /* GPP_G1 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_G1, NONE), - - /* GPP_G2 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_G2, NONE), - - /* GPP_G3 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_G3, NONE), - - /* GPP_G4 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_G4, NONE), - - /* GPP_G5 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ - PAD_NC(GPP_G5, UP_20K), - - /* GPP_G6 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_G6, NONE), - - /* GPP_G7 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00001000 */ - PAD_NC(GPP_G7, DN_20K), - - /* ------- GPIO Community 1 ------- */ - - /* ------- GPIO Group GPP_D ------- */ - - /* GPP_D0 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_D0, NONE), - - /* GPP_D1 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_D1, NONE), - - /* GPP_D2 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_D2, NONE), - - /* GPP_D3 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_D3, NONE), - - /* GPP_D4 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_D4, NONE), - - /* GPP_D5 - ISH_I2C0_SDA */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), - - /* GPP_D6 - ISH_I2C0_SCL */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - - /* GPP_D7 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D7, 1, PLTRST), - - /* GPP_D8 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D8, 0, PLTRST), - - /* GPP_D9 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D9, 1, PLTRST), - - /* GPP_D10 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D10, 1, PLTRST), - - /* GPP_D11 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00003000 */ - PAD_CFG_TERM_GPO(GPP_D11, 1, UP_20K, DEEP), - - /* GPP_D12 - GPIO */ - /* DW0: 0x42100102, DW1: 0x00003000 */ - PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE), - - /* GPP_D13 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D13, 1, RSMRST), - - /* GPP_D14 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D14, 1, PLTRST), - - /* GPP_D15 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), - - /* GPP_D16 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D16, 0, RSMRST), - - /* GPP_D17 - DMIC_CLK1 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), - - /* GPP_D18 - DMIC_DATA1 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), - - /* GPP_D19 - DMIC_CLK0 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), - - /* GPP_D20 - DMIC_DATA0 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), - - /* GPP_D21 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_D21, NONE), - - /* GPP_D22 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_D22, NONE), - - /* GPP_D23 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_D23, NONE), - - /* ------- GPIO Group GPP_F ------- */ - - /* GPP_F0 - GPIO */ - /* DW0: 0x00000301, DW1: 0x00000000 */ - PAD_NC(GPP_F0, NONE), - - /* GPP_F1 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_F1, 0, RSMRST), - - /* GPP_F2 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00003000 */ - PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), - - /* GPP_F3 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00003000 */ - PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST), - - /* GPP_F4 - CNV_BRI_DT */ - /* DW0: 0x44000700, DW1: 0x00003000 */ - PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1), - - /* GPP_F5 - CNV_BRI_RSP */ - /* DW0: 0x44000702, DW1: 0x00003000 */ - PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), - - /* GPP_F6 - CNV_RGI_DT */ - /* DW0: 0x44000700, DW1: 0x00003000 */ - PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), - - /* GPP_F7 - CNV_RGI_RSP */ - /* DW0: 0x44000702, DW1: 0x00003000 */ - PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), - - /* GPP_F8 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F8, NONE), - - /* GPP_F9 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F9, NONE), - - /* GPP_F10 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_F10, 1, PLTRST), - - /* GPP_F11 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F11, NONE), - - /* GPP_F12 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F12, NONE), - - /* GPP_F13 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F13, NONE), - - /* GPP_F14 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F14, NONE), - - /* GPP_F15 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F15, NONE), - - /* GPP_F16 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F16, NONE), - - /* GPP_F17 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F17, NONE), - - /* GPP_F18 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F18, NONE), - - /* GPP_F19 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F19, NONE), - - /* GPP_F20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F20, NONE), - - /* GPP_F21 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F21, NONE), - - /* GPP_F22 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_F22, NONE), - - /* GPP_F23 - A4WP_PRESENT */ - /* DW0: 0x44000700, DW1: 0x00001000 */ - PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1), - - /* ------- GPIO Group GPP_H ------- */ - - /* GPP_H0 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ - PAD_NC(GPP_H0, UP_20K), - - /* GPP_H1 - CNV_RF_RESET# */ - /* DW0: 0x44000f00, DW1: 0x00003000 */ - PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3), - - /* GPP_H2 - MODEM_CLKREQ */ - /* DW0: 0x44000f00, DW1: 0x00003000 */ - PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3), - - /* GPP_H3 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ - PAD_NC(GPP_H3, UP_20K), - - /* GPP_H4 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_H4, NONE), - - /* GPP_H5 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_H5, NONE), - - /* GPP_H6 - I2C3_SDA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - - /* GPP_H7 - I2C3_SCL */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - - /* GPP_H8 - I2C4_SDA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - - /* GPP_H9 - I2C4_SCL */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), - - /* GPP_H10 - I2C5_SDA */ - /* DW0: 0x84000603, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1), - - /* GPP_H11 - I2C5_SCL */ - /* DW0: 0x84000603, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1), - - /* GPP_H12 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H12, 1, PLTRST), - - /* GPP_H13 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H13, 1, PLTRST), - - /* GPP_H14 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H14, 0, PLTRST), - - /* GPP_H15 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H15, 1, PLTRST), - - /* GPP_H16 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H16, 1, RSMRST), - - /* GPP_H17 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H17, 1, RSMRST), - - /* GPP_H18 - CPU_C10_GATE# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), - - /* GPP_H19 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H19, 1, PLTRST), - - /* GPP_H20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_H20, NONE), - - /* GPP_H21 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H21, 0, DEEP), - - /* GPP_H22 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H22, 1, PLTRST), - - /* GPP_H23 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H23, 0, DEEP), - - /* ------- GPIO Community 2 ------- */ - - /* ------- GPIO Group GPD ------- */ - - /* GPD0 - BATLOW# */ - /* DW0: 0x04000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), - - /* GPD1 - ACPRESENT */ - /* DW0: 0x04000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), - - /* GPD2 - LAN_WAKE# */ - /* DW0: 0x04000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), - - /* GPD3 - PRWBTN# */ - /* DW0: 0x04000702, DW1: 0x00003000 */ - PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), - - /* GPD4 - SLP_S3# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), - - /* GPD5 - SLP_S4# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), - - /* GPD6 - SLP_A# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), - - /* GPD7 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPD7, 0, RSMRST), - - /* GPD8 - SUSCLK */ - /* DW0: 0x04000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), - - /* GPD9 - SLP_WLAN# */ - /* DW0: 0x04000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), - - /* GPD10 - SLP_S5# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), - - /* GPD11 - LANPHYPC */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), - - /* ------- GPIO Community 4 ------- */ - - /* ------- GPIO Group GPP_C ------- */ - - /* GPP_C0 - SMBCLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - - /* GPP_C1 - SMBDATA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - - /* GPP_C2 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_C2, 1, DEEP), - - /* GPP_C3 - SML0CLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - - /* GPP_C4 - SML0DATA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - - /* GPP_C5 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_C5, 1, PLTRST), - - /* GPP_C6 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_C6, NONE), - - /* GPP_C7 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_C7, NONE), - - /* GPP_C8 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_C8, 1, PLTRST), - - /* GPP_C9 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_C9, 1, PLTRST), - - /* GPP_C10 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_C10, 0, PLTRST), - - /* GPP_C11 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_C11, 1, PLTRST), - - /* GPP_C12 - UART1_RXD */ - /* DW0: 0x84000603, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), - - /* GPP_C13 - UART1_TXD */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), - - /* GPP_C14 - UART1_RTS# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), - - /* GPP_C15 - UART1_CTS# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), - - /* GPP_C16 - I2C0_SDA */ - /* DW0: 0x84000402, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), - - /* GPP_C17 - I2C0_SCL */ - /* DW0: 0x84000402, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), - - /* GPP_C18 - I2C1_SDA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - - /* GPP_C19 - I2C1_SCL */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - - /* GPP_C20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_C20, NONE), - - /* GPP_C21 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_C21, NONE), - - /* GPP_C22 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_C22, 1, PLTRST), - - /* GPP_C23 - GPIO */ - /* DW0: 0x40100102, DW1: 0x00001000 */ - PAD_CFG_GPI_APIC(GPP_C23, DN_20K, DEEP, LEVEL, NONE), - - /* ------- GPIO Group GPP_E ------- */ - - /* GPP_E0 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_E0, NONE), - - /* GPP_E1 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_E1, NONE), - - /* GPP_E2 - SATAXPCIE2 */ - /* DW0: 0x84000502, DW1: 0x00003000 */ - PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), - - /* GPP_E3 - GPIO */ - /* DW0: 0x82040102, DW1: 0x00000000 */ - PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), - - /* GPP_E4 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_E4, 1, PLTRST), - - /* GPP_E5 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_E5, NONE), - - /* GPP_E6 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ - PAD_NC(GPP_E6, NONE), - - /* GPP_E7 - GPIO */ - /* DW0: 0x82000102, DW1: 0x00000000 */ - PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, EDGE_SINGLE, ACPI), - - /* GPP_E8 - SATALED# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), - - /* GPP_E9 - RESERVED */ - /* DW0: 0x44001700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF5), - - /* GPP_E10 - RESERVED */ - /* DW0: 0x44001700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF5), - - /* GPP_E11 - USB2_OC2# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), - - /* GPP_E12 - USB2_OC3# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), - - /* GPP_E13 - DDPB_HPD0 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), - - /* GPP_E14 - DDPC_HPD1 */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - - /* GPP_E15 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_E15, 1, PLTRST), - - /* GPP_E16 - GPIO */ - /* DW0: 0x80880102, DW1: 0x00003000 */ - PAD_CFG_GPI_SCI(GPP_E16, UP_20K, PLTRST, LEVEL, INVERT), - - /* GPP_E17 - EDP_HPD */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), - - /* GPP_E18 - DPPB_CTRLCLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), - - /* GPP_E19 - DPPB_CTRLDATA */ - /* DW0: 0x44000602, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), - - /* GPP_E20 - DPPC_CTRLCLK */ - /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), - - /* GPP_E21 - DPPC_CTRLDATA */ - /* DW0: 0x44000602, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - - /* GPP_E22 - DPPD_CTRLCLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), - - /* GPP_E23 - DPPD_CTRLDATA */ - /* DW0: 0x44000602, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), -}; - -const struct pad_config *variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c deleted file mode 100644 index c3daf3c5ed..0000000000 --- a/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - 0x10ec0269, /* Codec Vendor/Device ID: Realtek ALC293 */ - 0x10ec0000, /* Subsystem ID */ - 11, /* Number of entries */ - - AZALIA_SUBVENDOR(0, 0x10ec0000), - AZALIA_PIN_CFG(0, 0x12, 0x40000000), - AZALIA_PIN_CFG(0, 0x15, 0x01214010), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x01a19130), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x40422201), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - - 0x8086280b, /* Codec Vendor/Device ID: Intel CannonPoint HDMI */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of entries */ - - AZALIA_SUBVENDOR(2, 0x80860101), - AZALIA_PIN_CFG(2, 0x05, 0x18560010), - AZALIA_PIN_CFG(2, 0x06, 0x18560020), - AZALIA_PIN_CFG(2, 0x07, 0x18560030), -}; - -const u32 pc_beep_verbs[] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h b/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h deleted file mode 100644 index 9094b0419d..0000000000 --- a/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <soc/gpe.h> -#include <soc/gpio.h> - -const struct pad_config *variant_gpio_table(size_t *num); - -#endif |