aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/msi/ms7260/romstage.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/msi/ms7260/romstage.c')
-rw-r--r--src/mainboard/msi/ms7260/romstage.c8
1 files changed, 1 insertions, 7 deletions
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 9804518c0d..210ea4f8fe 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -28,12 +28,6 @@
#define SET_NB_CFG_54 1
#endif
-/* Used by init_cpus and fidvid. */
-#define SET_FIDVID 1
-
-/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -201,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Set up chains and store link pair for optimization later. */
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr = rdmsr(0xc0010042);
print_debug("begin msr fid, vid ");