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-rw-r--r--src/mainboard/lippert/frontrunner/Config.lb34
-rw-r--r--src/mainboard/lippert/roadrunner-lx/Config.lb36
-rw-r--r--src/mainboard/lippert/spacerunner-lx/Config.lb35
3 files changed, 3 insertions, 102 deletions
diff --git a/src/mainboard/lippert/frontrunner/Config.lb b/src/mainboard/lippert/frontrunner/Config.lb
index 7dfa0ac556..6859b6a4fa 100644
--- a/src/mainboard/lippert/frontrunner/Config.lb
+++ b/src/mainboard/lippert/frontrunner/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/lippert/roadrunner-lx/Config.lb b/src/mainboard/lippert/roadrunner-lx/Config.lb
index 48436c62a1..d47b5c1897 100644
--- a/src/mainboard/lippert/roadrunner-lx/Config.lb
+++ b/src/mainboard/lippert/roadrunner-lx/Config.lb
@@ -20,41 +20,7 @@
## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/lippert/spacerunner-lx/Config.lb b/src/mainboard/lippert/spacerunner-lx/Config.lb
index 8ea92d01e8..98c3b22095 100644
--- a/src/mainboard/lippert/spacerunner-lx/Config.lb
+++ b/src/mainboard/lippert/spacerunner-lx/Config.lb
@@ -20,40 +20,7 @@
## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture