diff options
Diffstat (limited to 'src/mainboard/lenovo/x60')
| -rw-r--r-- | src/mainboard/lenovo/x60/romstage.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1198fb2007..1d9f68b5f2 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -29,6 +29,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <arch/acpi.h> #include <cbmem.h> #include <timestamp.h> #include <pc80/mc146818rtc.h> @@ -266,17 +267,16 @@ void main(unsigned long bist) reg32 = inl(DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); if (((reg32 >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } } /* Enable SPD ROMs and DDR-II DRAM */ |