diff options
Diffstat (limited to 'src/mainboard/lenovo/x220/romstage.c')
| -rw-r--r-- | src/mainboard/lenovo/x220/romstage.c | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 33d9b5e00e..a516ee617c 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -37,6 +37,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include "gpio.h" static void pch_enable_lpc(void) { @@ -128,17 +129,7 @@ void main(unsigned long bist) pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - outl(0x3963a5ff, DEFAULT_GPIOBASE); - outl(0x9ebf6aff, DEFAULT_GPIOBASE + 4); - outl(0x66ff7ffb, DEFAULT_GPIOBASE + 0xc); - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); - outl(0x00002043, DEFAULT_GPIOBASE + 0x2c); - outl(0x02ff04fe, DEFAULT_GPIOBASE + 0x30); - outl(0x1f47fbf5, DEFAULT_GPIOBASE + 0x34); - outl(0xbdecff87, DEFAULT_GPIOBASE + 0x38); - outl(0x000000f0, DEFAULT_GPIOBASE + 0x40); - outl(0x00000ff0, DEFAULT_GPIOBASE + 0x44); - outl(0x00000fcf, DEFAULT_GPIOBASE + 0x48); + setup_pch_gpios(&x220_gpio_map); early_usb_init((struct southbridge_usb_port []) { { 1, 0, 0 }, |