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-rw-r--r--src/mainboard/lenovo/t520/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index 40b005deb6..a1e24d525b 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
- register "c2_latency" = "101" # c2 not supported
-
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
register "spi_uvscc" = "0x2005"