diff options
Diffstat (limited to 'src/mainboard/lenovo/g505s')
| -rw-r--r-- | src/mainboard/lenovo/g505s/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/lenovo/g505s/devicetree.cb | 14 | ||||
| -rw-r--r-- | src/mainboard/lenovo/g505s/dsdt.asl | 4 |
3 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 07dbd1fdc7..cfb96159b3 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -19,8 +19,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select AGESA_LEGACY_WRAPPER - select CPU_AMD_AGESA_FAMILY15_RL - select NORTHBRIDGE_AMD_AGESA_FAMILY15_RL + select CPU_AMD_AGESA_FAMILY15_TN + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index a1cf338161..b12ab370b5 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -12,19 +12,19 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family15rl/root_complex +chip northbridge/amd/agesa/family15tn/root_complex device cpu_cluster 0 on - chip cpu/amd/agesa/family15rl + chip cpu/amd/agesa/family15tn device lapic 10 on end end end device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15rl # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - chip northbridge/amd/agesa/family15rl # PCI side of HT root complex + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX @@ -37,7 +37,7 @@ chip northbridge/amd/agesa/family15rl/root_complex device pci 7.0 off end # device pci 8.0 off end # NB/SB Link P2P bridge ? device pci 9.0 off end # - end #chip northbridge/amd/agesa/family15rl # PCI side of HT root complex + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus device pci 10.0 off end # FCH USB XHCI Controller HC0 (N.B. breaks EHCI debug!!!) @@ -84,6 +84,6 @@ chip northbridge/amd/agesa/family15rl/root_complex { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" - end #chip northbridge/amd/agesa/family15rl # CPU side of HT root complex + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain -end #chip northbridge/amd/agesa/family15rl/root_complex +end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl index 74b67f7c39..e486fef6fd 100644 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ b/src/mainboard/lenovo/g505s/dsdt.asl @@ -38,7 +38,7 @@ DefinitionBlock ( #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> /* Describe the processor tree (\_PR) */ - #include <cpu/amd/agesa/family15rl/acpi/cpu.asl> + #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> /* Describe the supported Sleep States for this Southbridge */ #include <southbridge/amd/common/acpi/sleepstates.asl> @@ -55,7 +55,7 @@ DefinitionBlock ( Device(PCI0) { /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family15rl/acpi/northbridge.asl> + #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> /* Describe the AMD Fusion Controller Hub Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/fch.asl> |