diff options
Diffstat (limited to 'src/mainboard/kontron')
| -rw-r--r-- | src/mainboard/kontron/ktqm77/devicetree.cb | 23 | ||||
| -rw-r--r-- | src/mainboard/kontron/ktqm77/early_init.c | 51 |
2 files changed, 26 insertions, 48 deletions
diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index e07cdf299e..853a410247 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -2,6 +2,29 @@ chip northbridge/intel/sandybridge # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "max_mem_clock_mhz" = "800" + register "ec_present" = "1" + + register "usb3.hs_port_switch_mask" = "0xf" + register "usb3.mode" = "3" + register "usb3.preboot_support" = "1" + register "usb3.xhci_streams" = "1" + register "usb_port_config" = "{ + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 4, 0x0040 }, + { 1, 4, 0x0040 }, + { 1, 4, 0x0040 }, + { 1, 4, 0x0040 }, + { 1, 4, 0x0040 }, + { 1, 4, 0x0040 }, }" + chip cpu/intel/model_206ax device cpu_cluster 0 on end diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index 43cd7ac475..e8fa6b1d69 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -55,54 +55,9 @@ void bootblock_mainboard_early_init(void) void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, - .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, - .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, - .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_BASE_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled USB oc pin length */ - { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */ - { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */ - { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */ - { 1, 0, 0x0040 }, /* P3: upper right USB 3.0 (OC0) */ - { 1, 0, 0x0040 }, /* P4: lower USB 2.0 (OC0) */ - { 1, 0, 0x0040 }, /* P5: upper USB 2.0 (OC0) */ - { 1, 0, 0x0040 }, /* P6: front panel USB 2.0 (OC0) */ - { 1, 0, 0x0040 }, /* P7: front panel USB 2.0 (OC0) */ - { 1, 4, 0x0040 }, /* P8: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P9: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P10: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P11: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P12: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P13: internal USB 2.0 (OC4) */ - }, - .usb3 = { - .mode = 3, /* Smart Auto? */ - .hs_port_switch_mask = 0xf, /* All four ports. */ - .preboot_support = 1, /* preOS driver? */ - .xhci_streams = 1, /* Enable. */ - }, - .pcie_init = 1, - }; - *pei_data = pei_data_template; + const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00}; + + memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); } const struct southbridge_usb_port mainboard_usb_ports[] = { |