3 files changed, 7 insertions, 4 deletions
diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c
index 37c3ab4186..845561026d 100644
--- a/src/mainboard/jetway/j7f2/romstage.c
+++ b/src/mainboard/jetway/j7f2/romstage.c
@@ -31,6 +31,7 @@
 #include "drivers/pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "southbridge/via/vt8237r/early_smbus.c"
+#include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71805f/f71805f.h>
 #include <lib.h>
 #include <spd.h>
@@ -90,7 +91,7 @@ void main(unsigned long bist)
 	/* Enable multifunction for northbridge. */
 	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 
-	f71805f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	enable_smbus();
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 3406edfde9..3e962d3274 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -40,7 +40,8 @@
 #include <cpu/amd/mtrr.h>
 #include <sb_cimx.h>
 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include "superio/fintek/f71869ad/f71869ad.h"
+#include <superio/fintek/common/fintek.h>
+#include <superio/fintek/f71869ad/f71869ad.h>
 
 /* FIXME: should not include .c files */
 #include "drivers/pc80/i8254.c"
@@ -75,7 +76,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		sb_Poweron_Init();
 
 		post_code(0x31);
-		f71869ad_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+		fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 		console_init();
 	}
 
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index c082a67646..044d0d8b0f 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -42,6 +42,7 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
+#include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71863fg/f71863fg.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -102,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb7xx_51xx_lpc_init();
 
-	f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();