diff options
Diffstat (limited to 'src/mainboard/iwill/dk8x')
| -rw-r--r-- | src/mainboard/iwill/dk8x/Kconfig | 51 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8x/Kconfig.name | 2 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8x/board_info.txt | 2 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8x/cmos.layout | 60 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8x/devicetree.cb | 56 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8x/irq_tables.c | 56 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8x/mptable.c | 166 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8x/romstage.c | 164 |
8 files changed, 0 insertions, 557 deletions
diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig deleted file mode 100644 index f2660c659c..0000000000 --- a/src/mainboard/iwill/dk8x/Kconfig +++ /dev/null @@ -1,51 +0,0 @@ -if BOARD_IWILL_DK8X - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_SOCKET_940 - select NORTHBRIDGE_AMD_AMDK8 - select SOUTHBRIDGE_AMD_AMD8111 - select SOUTHBRIDGE_AMD_AMD8131 - select SUPERIO_WINBOND_W83627THG - select PARALLEL_CPU_INIT - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select BOARD_ROMSIZE_KB_512 - select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT - -config MAINBOARD_DIR - string - default iwill/dk8x - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "DK8X" - -config MAX_CPUS - int - default 2 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x20 - -config HT_CHAIN_UNITID_BASE - hex - default 0x1 - -config IRQ_SLOT_COUNT - int - default 9 - -endif # BOARD_IWILL_DK8X diff --git a/src/mainboard/iwill/dk8x/Kconfig.name b/src/mainboard/iwill/dk8x/Kconfig.name deleted file mode 100644 index a474a76516..0000000000 --- a/src/mainboard/iwill/dk8x/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_IWILL_DK8X - bool "DK8X" diff --git a/src/mainboard/iwill/dk8x/board_info.txt b/src/mainboard/iwill/dk8x/board_info.txt deleted file mode 100644 index 0a80c2b4e0..0000000000 --- a/src/mainboard/iwill/dk8x/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: server -Board URL: http://web.archive.org/web/20060213163325/http://www.iwill.net/product_2.asp?p_id=28 diff --git a/src/mainboard/iwill/dk8x/cmos.layout b/src/mainboard/iwill/dk8x/cmos.layout deleted file mode 100644 index 4e081ea1aa..0000000000 --- a/src/mainboard/iwill/dk8x/cmos.layout +++ /dev/null @@ -1,60 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/iwill/dk8x/devicetree.cb b/src/mainboard/iwill/dk8x/devicetree.cb deleted file mode 100644 index d92cd6d5fd..0000000000 --- a/src/mainboard/iwill/dk8x/devicetree.cb +++ /dev/null @@ -1,56 +0,0 @@ -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end - device domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 on end - device pci 1.0 off end - end - device pci 1.0 on - # TODO: This is incomplete. - chip superio/winbond/w83627thg - device pnp 2e.0 on end - device pnp 2e.1 on end - device pnp 2e.2 on end - device pnp 2e.3 on end - device pnp 2e.5 on end - device pnp 2e.7 on end - device pnp 2e.8 on end - device pnp 2e.9 on end - device pnp 2e.a on end - device pnp 2e.b on end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on end - device pci 1.5 off end - device pci 1.6 off end - end - end # LDT0 - device pci 18.0 on end # LDT1 - device pci 18.0 on end # LDT2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/iwill/dk8x/irq_tables.c b/src/mainboard/iwill/dk8x/irq_tables.c deleted file mode 100644 index 1b7b92bfc6..0000000000 --- a/src/mainboard/iwill/dk8x/irq_tables.c +++ /dev/null @@ -1,56 +0,0 @@ -#include <arch/pirq_routing.h> -#include <device/pci.h> - -#define IRQ_ROUTER_BUS 1 -#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3) -#define IRQ_ROUTER_VENDOR 0x1022 -#define IRQ_ROUTER_DEVICE 0x746b - -#define AVAILABLE_IRQS 0xdef8 -#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \ - { bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \ - {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} - -/* Each IRQ_SLOT entry consists of: - * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu - */ - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT - * devices on the bus */ - IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ - IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ - 0x00, /* IRQs devoted exclusively to PCI usage */ - IRQ_ROUTER_VENDOR, /* Vendor */ - IRQ_ROUTER_DEVICE, /* Device */ - 0x00, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x00, /* u8 checksum , mod 256 checksum must give - * zero, will be corrected later - */ - { - - /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */ - - /* PCI Slot 1-6 */ - IRQ_SLOT (1, 3,1,0, 2,3,4,1 ), - IRQ_SLOT (2, 3,2,0, 3,4,1,2 ), - IRQ_SLOT (3, 2,1,0, 2,3,4,1 ), - IRQ_SLOT (4, 2,2,0, 3,4,1,2 ), - IRQ_SLOT (5, 4,5,0, 2,3,4,1 ), - IRQ_SLOT (6, 4,4,0, 1,2,3,4 ), - - /* Onboard NICs */ - IRQ_SLOT (0, 2,3,0, 4,0,0,0 ), - IRQ_SLOT (0, 2,4,0, 4,0,0,0 ), - - /* Let Linux know about bus 1 */ - IRQ_SLOT (0, 1,4,3, 0,0,0,0 ), - } -}; -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c deleted file mode 100644 index b460ff7791..0000000000 --- a/src/mainboard/iwill/dk8x/mptable.c +++ /dev/null @@ -1,166 +0,0 @@ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - unsigned char bus_8131_1; - unsigned char bus_8131_2; - unsigned char bus_8111_1; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - { - device_t dev; - - /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); - bus_8111_1 = 4; - } - /* 8131-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); - bus_8131_1 = 2; - } - /* 8131-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); - bus_8131_2 = 3; - } - } - - mptable_write_buses(mc, NULL, &bus_isa); - - /* IOAPIC handling */ - smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR); - { - device_t dev; - struct resource *res; - /* 8131 apic 3 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x03, 0x11, - res2mmio(res, 0, 0)); - } - } - /* 8131 apic 4 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x04, 0x11, - res2mmio(res, 0, 0)); - } - } - } - - mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); - - /* Standard local interrupt assignments */ - mptable_lintsrc(mc, bus_isa); - - - /* PCI Slot 1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (1<<2)|0, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (1<<2)|1, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (1<<2)|2, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (1<<2)|3, 0x02, 0x10); - - /* PCI Slot 2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (2<<2)|0, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (2<<2)|1, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (2<<2)|2, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (2<<2)|3, 0x02, 0x11); - - /* PCI Slot 3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (1<<2)|0, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (1<<2)|1, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (1<<2)|2, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (1<<2)|3, 0x02, 0x10); - - /* PCI Slot 4 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (2<<2)|0, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (2<<2)|1, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (2<<2)|2, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (2<<2)|3, 0x02, 0x11); - - /* PCI Slot 5 */ - // FIXME get the irqs right, it's just hacked to work for now - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (5<<2)|0, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (5<<2)|1, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (5<<2)|2, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (5<<2)|3, 0x02, 0x10); - - /* PCI Slot 6 */ - // FIXME get the irqs right, it's just hacked to work for now - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (4<<2)|0, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (4<<2)|1, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (4<<2)|2, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (4<<2)|3, 0x02, 0x13); - - /* On board nics */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (3<<2)|0, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (4<<2)|0, 0x02, 0x13); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c deleted file mode 100644 index 273e9f12f9..0000000000 --- a/src/mainboard/iwill/dk8x/romstage.c +++ /dev/null @@ -1,164 +0,0 @@ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include <cpu/amd/model_fxx_rev.h> -#include "southbridge/amd/amd8111/early_smbus.c" -#include <northbridge/amd/amdk8/raminit.h> -#include "northbridge/amd/amdk8/reset_test.c" -#include <cpu/x86/bist.h> -#include <delay.h> -#include "northbridge/amd/amdk8/debug.c" -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/early_ctrl.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -/* - * GPIO28 of 8111 will control H0_MEMRESET_L - * GPIO29 of 8111 will control H1_MEMRESET_L - */ -static void memreset_setup(void) -{ - if (is_cpu_pre_c0()) { - /* Set the memreset low. */ - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); - /* Ensure the BIOS has control of the memory lines. */ - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); - } else { - /* Ensure the CPU has control of the memory lines. */ - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); - } -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ - if (is_cpu_pre_c0()) { - udelay(800); - /* Set memreset high. */ - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); - udelay(90); - } -} - -static void activate_spd_rom(const struct mem_controller *ctrl) { } - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include <northbridge/amd/amdk8/amdk8.h> -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit.c" -#include "lib/generic_sdram.c" -#include "northbridge/amd/amdk8/resourcemap.c" -#include "cpu/amd/dualcore/dualcore.c" -#include <spd.h> -#include "cpu/amd/model_fxx/init_cpus.c" -#include "cpu/amd/model_fxx/fidvid.c" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - static const uint16_t spd_addr[] = { - // first node - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, - - // second node - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, - }; - - struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - - setup_default_resource_map(); - - printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - - setup_coherent_ht_domain(); // routing table and start other core0 - - wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); -#endif - - /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - -#if CONFIG_SET_FIDVID - { - msr_t msr; - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } -#endif - - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } - - allow_all_aps_stop(bsp_apicid); - - //It's the time to set ctrl in sysinfo now; - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - enable_smbus(); - -#if 0 - dump_smbus_registers(); -#endif - - memreset_setup(); - - //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ - init_timer(); // Need to use TMICT to synchronize FID/VID - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - -#if 0 - dump_pci_devices(); -#endif - - post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now -} |