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-rw-r--r--src/mainboard/intel/archercity_crb/ramstage.c7
-rw-r--r--src/mainboard/intel/cedarisland_crb/ramstage.c8
2 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/intel/archercity_crb/ramstage.c b/src/mainboard/intel/archercity_crb/ramstage.c
index 38bf576dcd..be3cc90918 100644
--- a/src/mainboard/intel/archercity_crb/ramstage.c
+++ b/src/mainboard/intel/archercity_crb/ramstage.c
@@ -1,3 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <cpu/x86/smm.h>
#include <soc/ramstage.h>
+#include <soc/smmrelocate.h>
+
+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
+{
+ soc_ubox_store_resources(slots, size);
+}
diff --git a/src/mainboard/intel/cedarisland_crb/ramstage.c b/src/mainboard/intel/cedarisland_crb/ramstage.c
index d2ab2a7b57..ba8807b729 100644
--- a/src/mainboard/intel/cedarisland_crb/ramstage.c
+++ b/src/mainboard/intel/cedarisland_crb/ramstage.c
@@ -1,6 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <cpu/x86/smm.h>
#include <soc/ramstage.h>
+#include <soc/smmrelocate.h>
+
#include "include/gpio.h"
void mainboard_silicon_init_params(FSPS_UPD *params)
@@ -8,3 +11,8 @@ void mainboard_silicon_init_params(FSPS_UPD *params)
/* configure Lewisburg PCH GPIO controller after FSP-M */
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}
+
+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
+{
+ soc_ubox_store_resources(slots, size);
+}