4 files changed, 44 insertions, 73 deletions
diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb
index 885043649c..37304f2167 100644
--- a/src/mainboard/intel/dcp847ske/devicetree.cb
+++ b/src/mainboard/intel/dcp847ske/devicetree.cb
@@ -11,6 +11,25 @@ chip northbridge/intel/sandybridge
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
+	# 1333MHz RAM frequency
+	register "max_mem_clock_mhz" = "666"
+
+	register "usb_port_config" = "{
+		{1, 0, 0x0040},
+		{1, 0, 0x0040},
+		{1, 1, 0x0040},
+		{1, 1, 0x0040},
+		{1, 2, 0x0040},
+		{1, 2, 0x0040},
+		{1, 3, 0x0040},
+		{0, 3, 0x0040},
+		{0, 4, 0x0040},
+		{0, 4, 0x0040},
+		{0, 5, 0x0040},
+		{0, 5, 0x0040},
+		{0, 6, 0x0040},
+		{0, 6, 0x0040},	}"
+
 	device domain 0 on
 		device ref host_bridge on  end	# Host bridge
 		device ref peg10 off end	# PCIe Bridge for discrete graphics
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index e7b936ae35..d0decb4602 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -1,44 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/hpet.h>
 #include <stdint.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#if CONFIG(USE_NATIVE_RAMINIT)
-#include <northbridge/intel/sandybridge/raminit_native.h>
-#else
 #include <northbridge/intel/sandybridge/raminit.h>
-#endif
 #include <southbridge/intel/bd82x6x/pch.h>
 
-#if !CONFIG(USE_NATIVE_RAMINIT)
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 0,
-		.gbe_enable = 1,
-		.max_ddr3_freq = 1333,
-		.usb_port_config = {
-#define USB_CONFIG(enabled, current, ocpin) { enabled, ocpin, 0x040 * current }
-#include "usb.h"
-		},
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xa0, 0x00, 0xa2, 0x00};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
 }
-#endif
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index ea17cc8cce..a7f5d3bd3e 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -11,6 +11,23 @@ chip northbridge/intel/sandybridge
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
+	register "max_mem_clock_mhz" = "800"
+
+	register "usb_port_config" = "{
+		{ 1, 0, 0x0040 },
+		{ 1, 1, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 2, 0x0040 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 0, 4, 0x0000 },
+		{ 1, 6, 0x0040 },
+		{ 1, 5, 0x0040 }, }"
 
 	chip cpu/intel/model_206ax
 		device cpu_cluster 0 on end
diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c
index c697ef2bf3..853add4dd6 100644
--- a/src/mainboard/intel/emeraldlake2/early_init.c
+++ b/src/mainboard/intel/emeraldlake2/early_init.c
@@ -50,44 +50,9 @@ void bootblock_mainboard_early_init(void)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 0,
-		.max_ddr3_freq = 1600,
-		.usb_port_config = {
-			{ 1, 0, 0x0040 }, /* P0: Front port  (OC0) */
-			{ 1, 1, 0x0040 }, /* P1: Back port   (OC1) */
-			{ 1, 0, 0x0040 }, /* P2: MINIPCIE1   (no OC) */
-			{ 1, 0, 0x0040 }, /* P3: MMC         (no OC) */
-			{ 1, 2, 0x0040 }, /* P4: Front port  (OC2) */
-			{ 0, 0, 0x0000 }, /* P5: Empty */
-			{ 0, 0, 0x0000 }, /* P6: Empty */
-			{ 0, 0, 0x0000 }, /* P7: Empty */
-			{ 1, 4, 0x0040 }, /* P8: Back port   (OC4) */
-			{ 1, 4, 0x0040 }, /* P9: MINIPCIE3   (no OC) */
-			{ 1, 4, 0x0040 }, /* P10: BLUETOOTH  (no OC) */
-			{ 0, 4, 0x0000 }, /* P11: Empty */
-			{ 1, 6, 0x0040 }, /* P12: Back port  (OC6) */
-			{ 1, 5, 0x0040 }, /* P13: Back port  (OC5) */
-		},
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = { 0xa0, 0x00, 0xa4, 0x00 };
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {