diff options
Diffstat (limited to 'src/mainboard/intel/tglrvp')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 201983cc87..d01fdd6352 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -44,6 +44,10 @@ chip soc/intel/tigerlake register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + register "PcieRpSlotImplemented[2]" = "1" + register "PcieRpSlotImplemented[3]" = "1" + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpSlotImplemented[10]" = "1" # Enable RP LTR register "PcieRpLtrEnable[2]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index d76c0f530c..c0adcc3f50 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -45,6 +45,10 @@ chip soc/intel/tigerlake register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + register "PcieRpSlotImplemented[2]" = "1" + register "PcieRpSlotImplemented[3]" = "1" + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpSlotImplemented[10]" = "1" # Enable PR LTR register "PcieRpLtrEnable[2]" = "1" |