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Diffstat (limited to 'src/mainboard/intel/tglrvp/variants')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb1
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 2b159d53fe..b84fddc397 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -147,7 +147,6 @@ chip soc/intel/tigerlake
# Intel Common SoC Config
register "common_soc_config" = "{
- .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index e55a73c434..fcadcee990 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -151,7 +151,6 @@ chip soc/intel/tigerlake
# Intel Common SoC Config
register "common_soc_config" = "{
- .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,