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path: root/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
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Diffstat (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index c381d2ef7d..417f23f83f 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -109,6 +109,9 @@ chip soc/intel/tigerlake
register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0"
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
# Enable S0ix
register "s0ix_enable" = "1"