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path: root/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
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Diffstat (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 401077229a..1396d3ac82 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -38,8 +38,6 @@ chip soc/intel/tigerlake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
- register "PrmrrSize" = "0x10000000"
-
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[8]" = "1"