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-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 71fed875de..e541bfe5af 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -143,7 +143,9 @@ chip soc/intel/skylake
}"
# Skip coreboot MP Init
- register "use_fsp_mp_init" = "1"
+ register "common_soc_config" = "{
+ .use_fsp_mp_init = 1,
+ }"
# Enable x1 slot
register "PcieRpEnable[7]" = "1"