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-rw-r--r--src/mainboard/intel/mtarvon/Config.lb2
-rw-r--r--src/mainboard/intel/mtarvon/Options.lb4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/intel/mtarvon/Config.lb b/src/mainboard/intel/mtarvon/Config.lb
index 0613d7d369..e5e598214d 100644
--- a/src/mainboard/intel/mtarvon/Config.lb
+++ b/src/mainboard/intel/mtarvon/Config.lb
@@ -18,7 +18,7 @@
##
## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
diff --git a/src/mainboard/intel/mtarvon/Options.lb b/src/mainboard/intel/mtarvon/Options.lb
index 17ccf4bc64..c5f2782fd9 100644
--- a/src/mainboard/intel/mtarvon/Options.lb
+++ b/src/mainboard/intel/mtarvon/Options.lb
@@ -150,7 +150,7 @@ default CONFIG_HEAP_SIZE=0x8000
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
-default CONFIG_FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
##
## coreboot C code runs at this location in RAM
@@ -229,5 +229,5 @@ default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
# CBFS
#
#
-default CONFIG_CBFS=0
+default CONFIG_CBFS=1
end