diff options
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants')
4 files changed, 121 insertions, 137 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 9d4c0d9286..20ea0c16a5 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -4,43 +4,6 @@ chip soc/intel/skylake register "DspEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - # Enable PCIE slot - register "PcieRpEnable[5]" = "1" - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 - # RP6, uses CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - register "PcieRpEnable[6]" = "1" - register "PcieRpClkReqSupport[6]" = "1" - register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 - # RP7, uses CLK SRC 2 - register "PcieRpClkSrcNumber[6]" = "2" - - register "PcieRpEnable[7]" = "1" - register "PcieRpClkReqSupport[7]" = "1" - register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 - # RP8, uses CLK SRC 3 - register "PcieRpClkSrcNumber[7]" = "3" - - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - # RP9, uses CLK SRC 4 - register "PcieRpClkSrcNumber[8]" = "4" - - register "PcieRpEnable[13]" = "1" - register "PcieRpClkReqSupport[13]" = "1" - register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 - # RP14, uses CLK SRC 5 - register "PcieRpClkSrcNumber[13]" = "5" - - register "PcieRpEnable[16]" = "1" - register "PcieRpClkReqSupport[16]" = "1" - register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 - # RP17, uses CLK SRC 7 - register "PcieRpClkSrcNumber[16]" = "7" - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -111,6 +74,42 @@ chip soc/intel/skylake }" end device ref i2c4 off end + device ref pcie_rp6 on + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" + register "PcieRpClkSrcNumber[5]" = "1" + end + device ref pcie_rp7 on + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "2" + register "PcieRpClkSrcNumber[6]" = "2" + end + device ref pcie_rp8 on + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "3" + register "PcieRpClkSrcNumber[7]" = "3" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + register "PcieRpClkSrcNumber[8]" = "4" + end + device ref pcie_rp14 on + register "PcieRpEnable[13]" = "1" + register "PcieRpClkReqSupport[13]" = "1" + register "PcieRpClkReqNumber[13]" = "5" + register "PcieRpClkSrcNumber[13]" = "5" + end + device ref pcie_rp17 on + register "PcieRpEnable[16]" = "1" + register "PcieRpClkReqSupport[16]" = "1" + register "PcieRpClkReqNumber[16]" = "7" + register "PcieRpClkSrcNumber[16]" = "7" + end device ref emmc off end device ref sdxc off end device ref hda on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 7de1454cca..6bca1215da 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -33,44 +33,6 @@ chip soc/intel/skylake .voltage_limit = 1520 }" - # Enable Root ports. - # PCIE Port 1 x4 -> SLOT1 - register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "2" - # RP1, uses CLK SRC 2 - register "PcieRpClkSrcNumber[0]" = "2" - - # PCIE Port 5 x1 -> SLOT2/LAN - register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqNumber[4]" = "3" - # RP5, uses CLK SRC 3 - register "PcieRpClkSrcNumber[4]" = "3" - - # PCIE Port 6 x1 -> SLOT3 - register "PcieRpEnable[5]" = "1" - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqNumber[5]" = "1" - # RP6, uses CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - # PCIE Port 7 Disabled - # PCIE Port 8 Disabled - # PCIE Port 9 x1 -> WLAN - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "5" - # RP9, uses CLK SRC 5 - register "PcieRpClkSrcNumber[8]" = "5" - - # PCIE Port 10 x1 -> WiGig - register "PcieRpEnable[9]" = "1" - register "PcieRpClkReqSupport[9]" = "1" - register "PcieRpClkReqNumber[9]" = "4" - # RP10, uses CLK SRC 4 - register "PcieRpClkSrcNumber[9]" = "4" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -113,11 +75,41 @@ chip soc/intel/skylake end device ref imgu on end device ref cio on end - device ref pcie_rp1 on end # x4 SLOT1 - device ref pcie_rp5 on end # x1 SLOT2/LAN - device ref pcie_rp6 on end # x1 SLOT3 - device ref pcie_rp9 on end # x1 WLAN - device ref pcie_rp10 on end # x1 WIGIG + device ref pcie_rp1 on + # PCIE x4 -> SLOT1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "2" + register "PcieRpClkSrcNumber[0]" = "2" + end + device ref pcie_rp5 on + # PCIE x1 -> SLOT2/LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + end + device ref pcie_rp6 on + # PCIE x1 -> SLOT3 + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" + register "PcieRpClkSrcNumber[5]" = "1" + end + device ref pcie_rp9 on + # PCIE x1 -> WLAN + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" + end + device ref pcie_rp10 on + # PCIE x1 -> WiGig + register "PcieRpEnable[9]" = "1" + register "PcieRpClkReqSupport[9]" = "1" + register "PcieRpClkReqNumber[9]" = "4" + register "PcieRpClkSrcNumber[9]" = "4" + end device ref lpc_espi on # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen2_dec" = "0x000c0201" diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 99963bf829..c4f8d46dbb 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -72,39 +72,6 @@ chip soc/intel/skylake .voltage_limit = 0 }" - # Enable Root ports. - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[8]" = "1" - - # Enable CLKREQ# - register "PcieRpClkReqSupport[2]" = "1" - register "PcieRpClkReqSupport[3]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - - # RP 3 uses SRCCLKREQ5# - register "PcieRpClkReqNumber[2]" = "5" - register "PcieRpClkReqNumber[3]" = "2" - register "PcieRpClkReqNumber[4]" = "3" - register "PcieRpClkReqNumber[5]" = "4" - register "PcieRpClkReqNumber[8]" = "1" - - # RP 3 uses CLK SRC 5# - register "PcieRpClkSrcNumber[2]" = "5" - # RP 4 uses CLK SRC 2# - register "PcieRpClkSrcNumber[3]" = "2" - # RP 5 uses CLK SRC 3# - register "PcieRpClkSrcNumber[4]" = "3" - # RP 6 uses CLK SRC 4# - register "PcieRpClkSrcNumber[5]" = "4" - # RP 9 uses CLK SRC 1# - register "PcieRpClkSrcNumber[8]" = "1" - - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -156,10 +123,36 @@ chip soc/intel/skylake [2] = 1, }" end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp5 on end - device ref pcie_rp6 on end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqNumber[2]" = "5" + register "PcieRpClkSrcNumber[2]" = "5" + end + device ref pcie_rp4 on + register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "2" + register "PcieRpClkSrcNumber[3]" = "2" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + end + device ref pcie_rp6 on + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "4" + register "PcieRpClkSrcNumber[5]" = "4" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "1" + end device ref lpc_espi on # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen2_dec" = "0x000c0201" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index eb13212a57..96bd56bdbf 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -75,24 +75,6 @@ chip soc/intel/skylake .voltage_limit = 0 }" - # Enable Root port. - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[16]" = "1" - - # Enable CLKREQ# - register "PcieRpClkReqSupport[3]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqSupport[16]" = "1" - - # SRCCLKREQ# - register "PcieRpClkReqNumber[3]" = "2" - register "PcieRpClkReqNumber[4]" = "1" - register "PcieRpClkReqNumber[8]" = "6" - register "PcieRpClkReqNumber[16]" = "7" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -165,8 +147,26 @@ chip soc/intel/skylake device ref i2c4 off end device ref pcie_rp1 off end device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp5 on end + device ref pcie_rp4 on + register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "2" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "1" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "6" + end + device ref pcie_rp17 on + register "PcieRpEnable[16]" = "1" + register "PcieRpClkReqSupport[16]" = "1" + register "PcieRpClkReqNumber[16]" = "7" + end device ref emmc off end device ref sdxc off end device ref lpc_espi on |