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path: root/src/mainboard/intel/adlrvp/early_gpio_m.c
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Diffstat (limited to 'src/mainboard/intel/adlrvp/early_gpio_m.c')
-rw-r--r--src/mainboard/intel/adlrvp/early_gpio_m.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c
index 79349b1be6..915240ce0c 100644
--- a/src/mainboard/intel/adlrvp/early_gpio_m.c
+++ b/src/mainboard/intel/adlrvp/early_gpio_m.c
@@ -12,6 +12,11 @@ static const struct pad_config early_gpio_table[] = {
/* WWAN_PWR_EN */
PAD_CFG_GPO(GPP_A8, 1, DEEP),
+ /* H0 : PCH_SSD_RST# */
+ PAD_CFG_GPO(GPP_H0, 0, PLTRST),
+ /* H13 : CPU_SSD_RST# */
+ PAD_CFG_GPO(GPP_H13, 0, PLTRST),
+
/* CPU PCIe VGPIO for RP0 */
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1),
@@ -111,6 +116,12 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
/* F12 : GSPI1_MOSI */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
+
+ /* D10 : PCH_SSD_PWR_EN */
+ PAD_CFG_GPO(GPP_D10, 1, PLTRST),
+ /* D16 : CPU_SSD_PWR_EN */
+ PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+
};
static const struct pad_config early_uart_gpio_table[] = {