4 files changed, 13 insertions, 34 deletions
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
index eae72aef4d..69e106e750 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
+++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
@@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select PIRQ_ROUTE
 	select BOARD_ROMSIZE_KB_256
 	select POWER_BUTTON_FORCE_ENABLE
+	select PLL_MANUAL_CONFIG
+	select CORE_GLIU_500_266
 
 config MAINBOARD_DIR
 	string
@@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT
 	int
 	default 9
 
+config PLLMSRlo
+	hex
+	default 0x00DE6000
+
 endif # BOARD_IEI_PCISA_LX_800_R10
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index aec984327a..7bd1b74ba1 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -41,14 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#define ManualConf 1		/* Do automatic strapped PLL config */
-//#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/
-//#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/
-#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/
-//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0
-/* Hold Count - how long we will sit in reset */
-#define PLLMSRlo 0x00DE6000
-
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
@@ -78,7 +70,7 @@ void main(unsigned long bist)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-	pll_reset(ManualConf);
+	pll_reset();
 
 	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig
index a897106e68..e443c6c8d6 100644
--- a/src/mainboard/iei/pm-lx-800-r11/Kconfig
+++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig
@@ -32,6 +32,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select PIRQ_ROUTE
 	select BOARD_ROMSIZE_KB_512
 	select POWER_BUTTON_FORCE_ENABLE
+	select PLL_MANUAL_CONFIG
+	select CORE_GLIU_500_266
 
 config MAINBOARD_DIR
 	string
@@ -45,19 +47,8 @@ config IRQ_SLOT_COUNT
 	int
 	default 7
 
-choice
-	prompt "Core/GLIU Frequency"
-	default CORE_GLIU_500_266
-
-config CORE_GLIU_500_266
-	bool "500MHz / 266MHz"
-
-config CORE_GLIU_500_333
-	bool "500MHz / 333MHz"
-
-config CORE_GLIU_500_400
-	bool "500MHz / 400MHz"
-
-endchoice
+config PLLMSRlo
+	hex
+	default 0x07de0000
 
 endif # BOARD_IEI_PM_LX_800_R11
diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c
index f7566221db..2992f53c12 100644
--- a/src/mainboard/iei/pm-lx-800-r11/romstage.c
+++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c
@@ -46,16 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#if CONFIG_CORE_GLIU_500_400
-#	define PLLMSRhi 0x0000059c
-#elif CONFIG_CORE_GLIU_500_333
-#	define PLLMSRhi 0x0000049c
-#else
-#	define PLLMSRhi 0x0000039c
-#endif
-
-#define PLLMSRlo 0x07de000
-
 #include <northbridge/amd/lx/raminit.h>
 #include <northbridge/amd/lx/pll_reset.c>
 #include <northbridge/amd/lx/raminit.c>
@@ -80,7 +70,7 @@ void main(unsigned long bist)
 
 	report_bist_failure(bist);
 
-	pll_reset(1);
+	pll_reset();
 
 	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);