diff options
Diffstat (limited to 'src/mainboard/google')
-rw-r--r-- | src/mainboard/google/veyron_brain/Kconfig | 4 | ||||
-rw-r--r-- | src/mainboard/google/veyron_brain/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/google/veyron_danger/Kconfig | 4 | ||||
-rw-r--r-- | src/mainboard/google/veyron_danger/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/google/veyron_jerry/Kconfig | 4 | ||||
-rw-r--r-- | src/mainboard/google/veyron_jerry/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/google/veyron_mighty/Kconfig | 4 | ||||
-rw-r--r-- | src/mainboard/google/veyron_mighty/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/google/veyron_pinky/Kconfig | 4 | ||||
-rw-r--r-- | src/mainboard/google/veyron_pinky/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/google/veyron_rialto/Kconfig | 4 | ||||
-rw-r--r-- | src/mainboard/google/veyron_rialto/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/google/veyron_speedy/Kconfig | 4 | ||||
-rw-r--r-- | src/mainboard/google/veyron_speedy/romstage.c | 2 |
14 files changed, 7 insertions, 35 deletions
diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig index 3539d1ee2b..f8902c9bd4 100644 --- a/src/mainboard/google/veyron_brain/Kconfig +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -56,10 +56,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 2048 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c index 3f9e7aaa4a..37efcaac6b 100644 --- a/src/mainboard/google/veyron_brain/romstage.c +++ b/src/mainboard/google/veyron_brain/romstage.c @@ -103,7 +103,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index 719064ef8e..294fd97023 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -57,10 +57,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 2048 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index c18471abe5..f3883bd28f 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -113,7 +113,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron_jerry/Kconfig index b9205ecaa7..7730aba89a 100644 --- a/src/mainboard/google/veyron_jerry/Kconfig +++ b/src/mainboard/google/veyron_jerry/Kconfig @@ -68,10 +68,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 2048 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index 1eed268fa7..9d19586cd5 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -112,7 +112,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig index 9bc571322c..5482e0f8e2 100644 --- a/src/mainboard/google/veyron_mighty/Kconfig +++ b/src/mainboard/google/veyron_mighty/Kconfig @@ -68,10 +68,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 2048 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index 1eed268fa7..9d19586cd5 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -112,7 +112,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index c3a47e54b0..0c991c7c28 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -68,10 +68,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 2048 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index ba96688705..74c5ef3585 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -120,7 +120,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 40b5c39d2e..8393895e16 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -64,10 +64,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 1024 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index c18471abe5..f3883bd28f 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -113,7 +113,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig index bbc3fc84ef..4d7f45d287 100644 --- a/src/mainboard/google/veyron_speedy/Kconfig +++ b/src/mainboard/google/veyron_speedy/Kconfig @@ -68,10 +68,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 2048 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c index c18471abe5..f3883bd28f 100644 --- a/src/mainboard/google/veyron_speedy/romstage.c +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -113,7 +113,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); |