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-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb1
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb1
3 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 5826f79ba9..7d9d1e64ca 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -20,7 +20,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SkipExtGfxScan" = "1"
register "SataSalpSupport" = "1"
- register "SataMode" = "SATA_AHCI"
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
# Configure devslp pad reset to PLT_RST
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 69e4e7d059..c975b9906c 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -16,7 +16,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "SataSalpSupport" = "1"
- register "SataMode" = "SATA_AHCI"
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1"
register "SkipExtGfxScan" = "1"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 021feba777..6a807a36b6 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -16,7 +16,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "SataSalpSupport" = "1"
- register "SataMode" = "SATA_AHCI"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1"