diff options
Diffstat (limited to 'src/mainboard/google')
-rw-r--r-- | src/mainboard/google/brya/variants/gaelin/gpio.c | 14 | ||||
-rw-r--r-- | src/mainboard/google/brya/variants/gaelin/overridetree.cb | 21 |
2 files changed, 27 insertions, 8 deletions
diff --git a/src/mainboard/google/brya/variants/gaelin/gpio.c b/src/mainboard/google/brya/variants/gaelin/gpio.c index 1438975b25..29abff3040 100644 --- a/src/mainboard/google/brya/variants/gaelin/gpio.c +++ b/src/mainboard/google/brya/variants/gaelin/gpio.c @@ -26,15 +26,15 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_B3, NONE), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, DEEP), - /* B7 : ISH_12C1_SDA ==> NC */ - PAD_NC(GPP_B7, NONE), - /* B8 : ISH_I2C1_SCL ==> NC */ - PAD_NC(GPP_B8, NONE), + /* B7 : ISH_I2C1_SDA ==> I2C_TCHSCR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_I2C1_SCL ==> I2C_TCHSCR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), - /* C6 : SML1CLK ==> USI_RST_L */ - PAD_CFG_GPO(GPP_C6, 0, DEEP), + /* C6 : SML1CLK ==> USI_EN_PWR */ + PAD_CFG_GPO(GPP_C6, 1, DEEP), /* C7 : SML1DATA ==> USI_INT_L */ - PAD_CFG_GPO(GPP_C7, 0, DEEP), + PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), /* D0 : ISH_GP0 ==> NC */ PAD_NC(GPP_D0, NONE), diff --git a/src/mainboard/google/brya/variants/gaelin/overridetree.cb b/src/mainboard/google/brya/variants/gaelin/overridetree.cb index 6a572d3f94..c36e983ac0 100644 --- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb +++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb @@ -13,7 +13,7 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" @@ -41,6 +41,7 @@ chip soc/intel/alderlake #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | + #| I2C3 | TouchScreen | #+-------------------+---------------------------+ register "common_soc_config" = "{ .i2c[0] = { @@ -53,6 +54,12 @@ chip soc/intel/alderlake .fall_time_ns = 400, .data_hold_time_ns = 50, }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, }" device domain 0 on @@ -184,6 +191,18 @@ chip soc/intel/alderlake device i2c 1a on end end # Audio Nau8825 end # I2C0 + device ref i2c3 on + chip drivers/i2c/hid + register "generic.hid" = ""LM230001"" + register "generic.desc" = ""LM238 Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)" + register "generic.enable_delay_ms" = "6" + register "generic.has_power_resource" = "1" + device i2c 34 on end + end + end # I2C3 device ref pcie_rp5 on # Enable PCIE 5 using clk 2 register "pch_pcie_rp[PCH_RP(5)]" = "{ |