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-rw-r--r--src/mainboard/google/butterfly/devicetree.cb16
-rw-r--r--src/mainboard/google/butterfly/early_init.c18
-rw-r--r--src/mainboard/google/link/devicetree.cb16
-rw-r--r--src/mainboard/google/link/early_init.c18
-rw-r--r--src/mainboard/google/parrot/devicetree.cb16
-rw-r--r--src/mainboard/google/parrot/early_init.c19
-rw-r--r--src/mainboard/google/stout/devicetree.cb16
-rw-r--r--src/mainboard/google/stout/early_init.c18
8 files changed, 0 insertions, 137 deletions
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index b8459c9009..cb34f3c55e 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -25,22 +25,6 @@ chip northbridge/intel/sandybridge
# Force double refresh rate
register "ddr_refresh_rate_config" = "DDR_REFRESH_RATE_DOUBLE"
- register "usb_port_config" = "{
- { 1, 0, 0x0040 },
- { 1, 0, 0x0040 },
- { 1, 0, 0x0040 },
- { 0, 0, 0x0000 },
- { 0, 0, 0x0000 },
- { 0, 0, 0x0000 },
- { 0, 0, 0x0000 },
- { 0, 0, 0x0000 },
- { 0, 4, 0x0000 },
- { 1, 4, 0x0080 },
- { 1, 4, 0x0040 },
- { 0, 4, 0x0000 },
- { 0, 4, 0x0000 },
- { 0, 4, 0x0000 },}"
-
device domain 0 on
device ref host_bridge on end # host bridge
device ref peg10 off end # PCIe Bridge for discrete graphics
diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c
index f63d3c3d75..8d07a38b14 100644
--- a/src/mainboard/google/butterfly/early_init.c
+++ b/src/mainboard/google/butterfly/early_init.c
@@ -44,24 +44,6 @@ void mainboard_late_rcba_config(void)
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
}
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- /* enabled power USB oc pin */
- { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */
- { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */
- { 1, 0, -1 }, /* P2: Camera (no OC) */
- { 0, 0, -1 }, /* P3: Empty */
- { 0, 0, -1 }, /* P4: Empty */
- { 0, 0, -1 }, /* P5: Empty */
- { 0, 0, -1 }, /* P6: Empty */
- { 0, 0, -1 }, /* P7: Empty */
- { 0, 0, -1 }, /* P8: Empty */
- { 1, 1, -1 }, /* P9: Left USB 1 (no OC) */
- { 1, 0, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */
- { 0, 0, -1 }, /* P11: Empty */
- { 0, 0, -1 }, /* P12: Empty */
- { 0, 0, -1 }, /* P13: Empty */
-};
-
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index f14728f643..028db5e528 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -22,22 +22,6 @@ chip northbridge/intel/sandybridge
# FIXME: Native raminit requires reduced max clock
register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
- register "usb_port_config" = "{
- { 0, 3, 0x0000 },
- { 1, 0, 0x0040 },
- { 1, 1, 0x0040 },
- { 1, 3, 0x0040 },
- { 0, 3, 0x0000 },
- { 1, 3, 0x0040 },
- { 0, 3, 0x0000 },
- { 0, 3, 0x0000 },
- { 1, 4, 0x0040 },
- { 1, 4, 0x0040 },
- { 0, 4, 0x0000 },
- { 0, 4, 0x0000 },
- { 0, 4, 0x0000 },
- { 0, 4, 0x0000 },}"
-
device domain 0 on
subsystemid 0x1ae0 0xc000 inherit
device ref host_bridge on end # host bridge
diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c
index e40531dac1..2d20ac03a9 100644
--- a/src/mainboard/google/link/early_init.c
+++ b/src/mainboard/google/link/early_init.c
@@ -63,24 +63,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
}
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- /* enabled power USB oc pin */
- { 0, 0, -1 }, /* P0: Empty */
- { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */
- { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */
- { 1, 0, -1 }, /* P3: SDCARD (no OC) */
- { 0, 0, -1 }, /* P4: Empty */
- { 1, 0, -1 }, /* P5: WWAN (no OC) */
- { 0, 0, -1 }, /* P6: Empty */
- { 0, 0, -1 }, /* P7: Empty */
- { 1, 0, -1 }, /* P8: Camera (no OC) */
- { 1, 0, -1 }, /* P9: Bluetooth (no OC) */
- { 0, 0, -1 }, /* P10: Empty */
- { 0, 0, -1 }, /* P11: Empty */
- { 0, 0, -1 }, /* P12: Empty */
- { 0, 0, -1 }, /* P13: Empty */
-};
-
void mb_get_spd_map(struct spd_info *spdi)
{
/* LINK has 2 channels of memory down */
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index 075e407862..1509f0a1cc 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -22,22 +22,6 @@ chip northbridge/intel/sandybridge
# FIXME: Native raminit requires reduced max clock
register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
- register "usb_port_config" = "{
- { 0, 3, 0x0000 },
- { 1, 0, 0x0040 },
- { 1, 1, 0x0040 },
- { 1, 1, 0x0040 },
- { 0, 3, 0x0000 },
- { 0, 3, 0x0000 },
- { 0, 3, 0x0000 },
- { 0, 3, 0x0000 },
- { 1, 4, 0x0040 },
- { 0, 4, 0x0000 },
- { 1, 4, 0x0040 },
- { 0, 4, 0x0000 },
- { 0, 4, 0x0000 },
- { 0, 4, 0x0000 },}"
-
device domain 0 on
device ref host_bridge on end # host bridge
device ref igd on end # vga controller
diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c
index f91b7d9f45..077cb64576 100644
--- a/src/mainboard/google/parrot/early_init.c
+++ b/src/mainboard/google/parrot/early_init.c
@@ -50,22 +50,3 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
{
/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
}
-
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- /* enabled power USB oc pin */
- { 0, 0, -1 }, /* P0: Empty */
- { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */
- { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */
- { 1, 0, 1 }, /* P3: Left USB 3 (OC1) */
- { 0, 0, -1 }, /* P4: Empty */
- { 0, 0, -1 }, /* P5: Empty */
- { 0, 0, -1 }, /* P6: Empty */
- { 0, 0, -1 }, /* P7: Empty */
- /* Empty and onboard Ports 8-13, set to un-used pin OC4 */
- { 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */
- { 0, 0, -1 }, /* P9: Empty */
- { 1, 0, -1 }, /* P10: Camera (no OC) */
- { 0, 0, -1 }, /* P11: Empty */
- { 0, 0, -1 }, /* P12: Empty */
- { 0, 0, -1 }, /* P13: Empty */
-};
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 36e8ba79f6..0211921c38 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -22,22 +22,6 @@ chip northbridge/intel/sandybridge
# FIXME: Native raminit requires reduced max clock
register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
- register "usb_port_config" = "{
- { 1, 0, 0x0040 },
- { 1, 0, 0x0040 },
- { 0, 1, 0x0000 },
- { 1, 1, 0x0040 },
- { 1, 1, 0x0040 },
- { 1, 1, 0x0040 },
- { 0, 1, 0x0000 },
- { 0, 1, 0x0000 },
- { 0, 5, 0x0000 },
- { 1, 4, 0x0040 },
- { 0, 5, 0x0000 },
- { 0, 5, 0x0000 },
- { 0, 5, 0x0000 },
- { 1, 5, 0x0040 },}"
-
register "usb3.mode" = "2" # Auto
register "usb3.hs_port_switch_mask" = "3" # Ports 0 & 1
register "usb3.preboot_support" = "0" # No PreOS boot support
diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c
index e6e6227646..178d270da7 100644
--- a/src/mainboard/google/stout/early_init.c
+++ b/src/mainboard/google/stout/early_init.c
@@ -90,21 +90,3 @@ void mainboard_early_init(int s3resume)
early_ec_init();
}
}
-
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- /* enabled USB oc pin length */
- {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */
- {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */
- {0, 0, 0}, /* P2: Empty */
- {1, 0, -1}, /* P3: Camera (no OC) */
- {1, 0, -1}, /* P4: WLAN (no OC) */
- {1, 0, -1}, /* P5: WWAN (no OC) */
- {0, 0, 0}, /* P6: Empty */
- {0, 0, 0}, /* P7: Empty */
- {0, 0, 0}, /* P8: Empty */
- {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */
- {0, 0, 0}, /* P10: Empty */
- {0, 0, 0}, /* P11: Empty */
- {0, 0, 0}, /* P12: Empty */
- {1, 0, -1}, /* P13: Bluetooth (no OC) */
-};
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 06:52:29 +0000