diff options
Diffstat (limited to 'src/mainboard/google/zork')
9 files changed, 119 insertions, 20 deletions
diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 02181fba13..320f668838 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -225,6 +225,22 @@ config VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW Minimum board version where the variant starts supporting active low power enable for WiFi. +config VARIANT_HAS_FPMCU + bool + default y if BOARD_GOOGLE_BERKNIP + default y if BOARD_GOOGLE_MORPHIUS + default n + help + Select y if any SKU of the board has a fingerprint sensor + +config VARIANT_MAX_BOARD_ID_BROKEN_FMPCU_POWER + int + default 4 if BOARD_GOOGLE_MORPHIUS + default 3 if BOARD_GOOGLE_BERKNIP + default 0 + help + Last board version that needs the extra delay for FPMCU init. + config VBOOT_STARTS_BEFORE_BOOTBLOCK bool "PSP verstage" default y if VBOOT diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c index a7636de702..ed058886ff 100644 --- a/src/mainboard/google/zork/bootblock.c +++ b/src/mainboard/google/zork/bootblock.c @@ -2,12 +2,16 @@ #include <bootblock_common.h> #include <baseboard/variants.h> +#include <acpi/acpi.h> void bootblock_mainboard_early_init(void) { size_t num_gpios; const struct soc_amd_gpio *gpios; + gpios = variant_bootblock_gpio_table(&num_gpios, acpi_get_sleep_type()); + program_gpios(gpios, num_gpios); + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { gpios = variant_early_gpio_table(&num_gpios); program_gpios(gpios, num_gpios); diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 9503d3762c..6d930d0e7a 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -247,12 +247,13 @@ static void mainboard_final(void *chip_info) gnvs = acpi_get_gnvs(); - if (gnvs) { gnvs->tmps = CTL_TDP_SENSOR_ID; gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; } + + finalize_gpios(acpi_get_sleep_type()); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 2398d07d74..e43ccdd8b9 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -30,7 +30,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC & FPMCU */ + /* S0iX SLP - (unused - goes to EC */ PAD_NC(GPIO_10), /* EC_IN_RW_OD */ PAD_GPI(GPIO_11, PULL_NONE), @@ -291,6 +291,16 @@ __weak void variant_pcie_gpio_configure(void) wifi_power_reset_configure_pre_v3(); } +__weak void finalize_gpios(int slp_typ) +{ +} + +const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) +{ + *size = 0; + return NULL; +} + static const struct soc_amd_gpio gpio_sleep_table[] = { /* PCIE_RST1_L */ PAD_GPO(GPIO_27, LOW), diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index a436d1c3d0..9e980dbe8b 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <baseboard/variants.h> #include <delay.h> +#include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/gpio.h> #include <soc/smi.h> @@ -32,8 +34,6 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), /* S0iX SLP - (unused - goes to EC & FPMCU */ PAD_NC(GPIO_10), - /* FPMCU_RST_L */ - PAD_GPO(GPIO_11, HIGH), /* USI_INT_ODL */ PAD_GPI(GPIO_12, PULL_NONE), /* EN_PWR_TOUCHPAD_PS2 */ @@ -71,8 +71,6 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_NONE), - /* EN_PWR_FP */ - PAD_GPO(GPIO_32, HIGH), /* GPIO_33 - GPIO_39: Not available */ /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), @@ -87,7 +85,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic /* EMMC_RESET_L */ PAD_GPO(GPIO_68, HIGH), - /* FPMCU_BOOT0 - TODO: Check this */ + /* FPMCU_BOOT0 */ PAD_GPO(GPIO_69, LOW), /* EMMC_CLK */ PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), @@ -300,6 +298,51 @@ __weak void variant_pcie_gpio_configure(void) wifi_power_reset_configure_pre_v3(); } +__weak void finalize_gpios(int slp_typ) +{ + if (variant_has_fingerprint() && slp_typ != ACPI_S3) { + + if (fpmcu_needs_delay()) + mdelay(550); + + /* + * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out + * of reset by setting FPMCU_RST_L high 3ms later. + */ + gpio_set(GPIO_32, 1); + mdelay(3); + gpio_set(GPIO_11, 1); + } +} + +static const struct soc_amd_gpio gpio_fingerprint_bootblock_table[] = { + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + +static const struct soc_amd_gpio gpio_no_fingerprint_bootblock_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_32), +}; + +const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) +{ + if (variant_has_fingerprint()) { + if (slp_typ == ACPI_S3) + return NULL; + + *size = ARRAY_SIZE(gpio_fingerprint_bootblock_table); + return gpio_fingerprint_bootblock_table; + } + + *size = ARRAY_SIZE(gpio_no_fingerprint_bootblock_table); + return gpio_no_fingerprint_bootblock_table; +} + static const struct soc_amd_gpio gpio_sleep_table[] = { /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index 70710351d2..d12a8ed407 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -149,3 +149,31 @@ int variant_get_daughterboard_id(void) { return extract_field(FW_CONFIG_MASK_DB_INDEX, FW_CONFIG_DB_INDEX_SHIFT); } + +bool variant_has_fingerprint(void) +{ + if (CONFIG(VARIANT_HAS_FPMCU)) + return true; + + return false; +} + +bool fpmcu_needs_delay(void) +{ + /* + * Older board versions need an extra delay here to finish resetting + * the FPMCU. The resistor value in the glitch prevention circuit was + * sized so that the FPMCU doesn't turn of for ~1 second. On newer + * boards, that's been updated to ~30ms, which allows the FPMCU's + * reset to be completed in the time between bootblock and finalize. + */ + uint32_t board_version; + + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version <= CONFIG_VARIANT_MAX_BOARD_ID_BROKEN_FMPCU_POWER) + return true; + + return false; +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 338b918623..4ec6addfe7 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -24,12 +24,17 @@ const struct soc_amd_gpio *variant_base_gpio_table(size_t *size); */ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size); +/* This function provides GPIO init in bootblock. */ +const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ); + /* * This function provides GPIO table for the pads that need to be configured when entering * sleep. */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); +/* Program any required GPIOs at the finalize phase */ +void finalize_gpios(int slp_typ); /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); /* Update audio configuration in devicetree during ramstage. */ @@ -69,9 +74,13 @@ bool variant_uses_v3_schematics(void); bool variant_uses_v3_6_schematics(void); /* Return true if variant uses CODEC_GPI pin for headphone jack interrupt. */ bool variant_uses_codec_gpi(void); -/* Return true if variant has active low power enable fow WiFi. */ +/* Return true if variant has active low power enable for WiFi. */ bool variant_has_active_low_wifi_power(void); /* Return value of daughterboard ID */ int variant_get_daughterboard_id(void); +/* Return true if the board has a fingerprint sensor. */ +bool variant_has_fingerprint(void); +/* Return true if the board needs an extra fpmcu delay. */ +bool fpmcu_needs_delay(void); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index d2dd104e89..f86d926e2e 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -37,8 +37,6 @@ static const struct soc_amd_gpio ezkinil_bid2_gpio_set_stage_ram[] = { PAD_NC(GPIO_4), /* PEN_POWER_EN - Not connected */ PAD_NC(GPIO_5), - /* FPMCU_RST_L Change NC */ - PAD_NC(GPIO_11), /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* EN_PWR_WIFI */ @@ -62,8 +60,6 @@ static const struct soc_amd_gpio ezkinil_bid3_gpio_set_stage_ram[] = { PAD_NC(GPIO_4), /* PEN_POWER_EN - Not connected */ PAD_NC(GPIO_5), - /* FPMCU_RST_L Change NC */ - PAD_NC(GPIO_11), /* FPMCU_BOOT0 Change NC */ PAD_NC(GPIO_69), /* EN_DEV_BEEP_L */ diff --git a/src/mainboard/google/zork/variants/woomax/gpio.c b/src/mainboard/google/zork/variants/woomax/gpio.c index cb98df7d41..329e7dddb3 100644 --- a/src/mainboard/google/zork/variants/woomax/gpio.c +++ b/src/mainboard/google/zork/variants/woomax/gpio.c @@ -10,10 +10,6 @@ static const struct soc_amd_gpio woomax_bid0_gpio_set_stage_ram[] = { PAD_NC(GPIO_5), /* GPIO_6 NC */ PAD_NC(GPIO_6), - /* GPIO_11 NC */ - PAD_NC(GPIO_11), - /* GPIO_32 NC */ - PAD_NC(GPIO_32), /* GPIO_69 NC */ PAD_NC(GPIO_69), /* RAM_ID_4 */ @@ -37,10 +33,6 @@ static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = { PAD_NC(GPIO_5), /* GPIO_6 NC */ PAD_NC(GPIO_6), - /* GPIO_11 NC */ - PAD_NC(GPIO_11), - /* GPIO_32 NC */ - PAD_NC(GPIO_32), /* GPIO_69 NC */ PAD_NC(GPIO_69), /* RAM_ID_4 */ |