5 files changed, 19 insertions, 19 deletions

diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig
index 97a009730a..7c4f084a99 100644
--- a/src/mainboard/google/veyron_pinky/Kconfig
+++ b/src/mainboard/google/veyron_pinky/Kconfig
@@ -61,14 +61,6 @@ config BOOT_MEDIA_SPI_BUS
         int
         default 2
 
-config DRAM_DMA_START
-	hex
-	default 0x10000000
-
-config DRAM_DMA_SIZE
-	hex
-	default 0x00200000
-
 config DRAM_SIZE_MB
 	int
 	default 2048
diff --git a/src/mainboard/google/veyron_pinky/Makefile.inc b/src/mainboard/google/veyron_pinky/Makefile.inc
index c33cfa3166..0cc89d0222 100644
--- a/src/mainboard/google/veyron_pinky/Makefile.inc
+++ b/src/mainboard/google/veyron_pinky/Makefile.inc
@@ -35,3 +35,8 @@ ramstage-y += boardid.c
 ramstage-y += chromeos.c
 ramstage-y += mainboard.c
 ramstage-y += reset.c
+
+bootblock-y += memlayout.ld
+verstage-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c
index 232010ddd9..19d66757ba 100644
--- a/src/mainboard/google/veyron_pinky/mainboard.c
+++ b/src/mainboard/google/veyron_pinky/mainboard.c
@@ -22,6 +22,7 @@
 #include <arch/cache.h>
 #include <delay.h>
 #include <edid.h>
+#include <symbols.h>
 #include <vbe.h>
 #include <boot/coreboot_tables.h>
 #include <device/i2c.h>
@@ -153,6 +154,6 @@ void lb_board(struct lb_header *header)
 	dma = (struct lb_range *)lb_new_record(header);
 	dma->tag = LB_TAB_DMA;
 	dma->size = sizeof(*dma);
-	dma->range_start = CONFIG_DRAM_DMA_START;
-	dma->range_size = CONFIG_DRAM_DMA_SIZE;
+	dma->range_start = (uintptr_t)_dma_coherent;
+	dma->range_size = _dma_coherent_size;
 }
diff --git a/src/mainboard/google/veyron_pinky/memlayout.ld b/src/mainboard/google/veyron_pinky/memlayout.ld
new file mode 100644
index 0000000000..a8b7465c5e
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/rockchip/rk3288/memlayout.ld>
diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c
index f972ee26c8..1d7812b3e0 100644
--- a/src/mainboard/google/veyron_pinky/romstage.c
+++ b/src/mainboard/google/veyron_pinky/romstage.c
@@ -35,6 +35,7 @@
 #include <soc/rockchip/rk3288/clock.h>
 #include <soc/rockchip/rk3288/pwm.h>
 #include <soc/rockchip/rk3288/grf.h>
+#include <symbols.h>
 #include "timer.h"
 
 static void regulate_vdd_log(unsigned int mv)
@@ -64,9 +65,9 @@ void main(void)
 	start_romstage_time = timestamp_get();
 #endif
 	/* used for MMU and CBMEM setup, in MB */
-	u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
-	u32 dram_size = CONFIG_DRAM_SIZE_MB;
-	u32 dram_end = dram_start + dram_size;
+	u32 dram_start_mb = (uintptr_t)_dram/MiB;
+	u32 dram_size_mb = CONFIG_DRAM_SIZE_MB;
+	u32 dram_end_mb = dram_start_mb + dram_size_mb;
 
 	console_init();
 
@@ -81,15 +82,15 @@ void main(void)
 #endif
 	mmu_init();
 	/* Device memory below DRAM is uncached. */
-	mmu_config_range(0, dram_start, DCACHE_OFF);
+	mmu_config_range(0, dram_start_mb, DCACHE_OFF);
 	/* DRAM is cached. */
-	mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
+	mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
 	/* A window for DMA is uncached. */
-	mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
-			 CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+	mmu_config_range((uintptr_t)_dma_coherent/MiB,
+			 _dma_coherent_size/MiB, DCACHE_OFF);
 	/* The space above DRAM is uncached. */
-	if (dram_end < 4096)
-		mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+	if (dram_end_mb < 4096)
+		mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
 	dcache_mmu_enable();
 
 	cbmem_initialize_empty();