diff options
Diffstat (limited to 'src/mainboard/google/rush_ryu/bootblock.c')
| -rw-r--r-- | src/mainboard/google/rush_ryu/bootblock.c | 48 |
1 files changed, 25 insertions, 23 deletions
diff --git a/src/mainboard/google/rush_ryu/bootblock.c b/src/mainboard/google/rush_ryu/bootblock.c index e5975d2dbc..ffcffd3634 100644 --- a/src/mainboard/google/rush_ryu/bootblock.c +++ b/src/mainboard/google/rush_ryu/bootblock.c @@ -23,6 +23,7 @@ #include <soc/addressmap.h> #include <soc/bootblock.h> #include <soc/clock.h> +#include <soc/funitcfg.h> #include <soc/padconfig.h> #include <soc/nvidia/tegra/i2c.h> #include <soc/nvidia/tegra132/clk_rst.h> @@ -30,8 +31,6 @@ #include "pmic.h" -static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; - static const struct pad_config uart_console_pads[] = { /* UARTA: tx and rx. */ PAD_CFG_SFIO(KB_ROW9, PINMUX_PULL_NONE, UA3), @@ -45,6 +44,26 @@ static const struct pad_config uart_console_pads[] = { PAD_CFG_UNUSED(UART2_CTS_N), }; +static const struct pad_config pmic_pads[] = { + PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU), + PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU), +}; + +static const struct pad_config spiflash_pads[] = { + /* mosi, miso, clk, cs0 */ + PAD_CFG_SFIO(GPIO_PG6, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4), + PAD_CFG_SFIO(GPIO_PG7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4), + PAD_CFG_SFIO(GPIO_PG5, PINMUX_INPUT_ENABLE, SPI4), + PAD_CFG_SFIO(GPIO_PI3, PINMUX_INPUT_ENABLE, SPI4), +}; + +static const struct funit_cfg funits[] = { + /* PMIC on I2C5 (PWR_I2C* pads) at 400kHz. */ + FUNIT_CFG(I2C5, PLLP, 400, pmic_pads, ARRAY_SIZE(pmic_pads)), + /* SPI flash at 33MHz on SPI4 controller. */ + FUNIT_CFG(SBC4, PLLP, 33333, spiflash_pads, ARRAY_SIZE(spiflash_pads)), +}; + void bootblock_mainboard_early_init(void) { soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads)); @@ -52,41 +71,24 @@ void bootblock_mainboard_early_init(void) static void set_clock_sources(void) { + struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta); - - clock_configure_source(mselect, PLLP, 102000); - - /* The PMIC is on I2C5 and can run at 400 KHz. */ - clock_configure_i2c_scl_freq(i2c5, PLLP, 400); - - /* TODO: We should be able to set this to 50MHz, but that did not seem - * reliable. */ - clock_configure_source(sbc4, PLLP, 33333); } static const struct pad_config padcfgs[] = { /* Board build id bits 1:0 */ PAD_CFG_GPIO_INPUT(KB_COL4, PINMUX_PULL_NONE), PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE), - /* PMIC i2C bus */ - PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU), - PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU), - /* SPI fLash: mosi, miso, clk, cs0 */ - PAD_CFG_SFIO(GPIO_PG6, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4), - PAD_CFG_SFIO(GPIO_PG7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4), - PAD_CFG_SFIO(GPIO_PG5, PINMUX_INPUT_ENABLE, SPI4), - PAD_CFG_SFIO(GPIO_PI3, PINMUX_INPUT_ENABLE, SPI4), }; void bootblock_mainboard_init(void) { set_clock_sources(); - /* Enable PMIC I2C controller. */ - clock_enable_clear_reset(0, CLK_H_I2C5, 0, 0, 0, 0); - - /* Set up the pads required to load romstage. */ + /* Set up controllers and pads to load romstage. */ + soc_configure_funits(funits, ARRAY_SIZE(funits)); soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs)); i2c_init(4); |